PM8611-BIAP PMC [PMC-Sierra, Inc], PM8611-BIAP Datasheet - Page 118

• Manufacturer Part Number: PM8611-BIAP
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010883, Issue 2
Register 049H: OMSU Interrupt Status and Memory Page Update Register
Writing to this register initiates an update of the off-line page in the time switch ram. The
contents of the on-line page are written to the off-line page. During this update, the time switch
ram may not be accessed through the indirect registers.
SWAP_PENDINGI
UPDATEI
Bit
Bit 2-14
Bit 1
Bit 0
The page swap pending interrupt status bit, SWAP_PENDINGI, reports and acknowledges a
change of state of the SWAP_PENDINGV bit of the MSU Configuration register. This bit is
cleared when this register is read. When enabled by the SWAP_PENDINGE bit, the INT
output reflects the state of this bit.
The off-line page update interrupt status bit, UPDATEI, reports and acknowledges a change
of state from high to low of the UPDATEV bit of the MSU Configuration register. This bit is
cleared when this register is read. When enabled by the UPDATEE bit, the INT output
reflects the state of this bit.
Type
R
R
SWAP_PENDINGI
UPDATEI
Function
Unused
SBSLITE™ Telecom Standard Product Data Sheet
Default
0
X
X
Preliminary
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