PM8611-BIAP PMC [PMC-Sierra, Inc], PM8611-BIAP Datasheet - Page 276

• Manufacturer Part Number: PM8611-BIAP
• Manufacturer: PMC [PMC-Sierra, Inc]

14.4
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010883, Issue 2
When switching DS0s in SBI mode, the minimum data delay through the SBSLITE increases to
an entire SBI336 frame or 9720 SYSCLK cycles. The actual delay will be slightly longer by no
more than 31 SYSCLK cycles to allow for other data path delays within the SBSLITE. The
Channel Associated Signaling delay through the SBSLITE will be two full T1 or E1 multiframes
which is 4mS for E1 links and 6mS for T1 links.
Figure 34 Incoming SBI Bus to LVDS Timing with DS0 Switching
The relative delay from the Incoming bus to either of the working and protect LVDS links may be
different but will be within a couple of SYSCLK cycles of each other.
Although Figure 33 and Figure 34 show IC1FP or IJ0J1V1 relative to SYSCLK, IC1FP(IJ0J1V1)
is sampled by SREFCLK.
Receive Serial LVDS Functional Timing
Figure 35 below shows the relative timing of the receive LVDS links. In TelecomBus mode links
carry SONET/SDH frame octets that are encoded in 8B/10B characters. Frame boundaries,
tributary justification events and tributary alarm conditions are encoded in special control
characters. The upstream devices sourcing the links share a common clock and have a common
transport frame alignment that is synchronized by the Receive Serial Interface Frame Pulse signal
(RC1FP). Due to phase noise of clock multiplication circuits and backplane routing
discrepancies, the links will not be phase aligned to each other (within a tolerance level of 24 byte
times) but are frequency locked The delay from RC1FP being sampled high to the first and last
J0 character is shown in Figure 35. In this example, the first J0 is delivered by the working link
(RNWRK/RPWRK). The delay to the last J0 represents the time when both links have delivered
their J0 character. The minimum value for the internal programmable delay (RC1FPDLY[13:0])
is the delay to the last J0 character plus 15. The maximum value is the delay to the first J0
character plus 31. Consequently, the external system must ensure that the relative delays between
all the receive LVDS links be less than 16 bytes. The relative phases of the links in Figure 35 are
shown for illustrative purposes only.
TNPROT/
TNWRK/
SYSCLK
TPPROT
TPWRK
TC1FP
IC1FP
IPL
...
...
Maximum Delay, 9720 + 31 cycles
Minimum Delay, 9720 + 23 cycles
Delay IC1FP to TC1FP, 9720 + 32 cycles
SBSLITE™ Telecom Standard Product Data Sheet
C1
...
...
C1
Preliminary
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