PM8611-BIAP PMC [PMC-Sierra, Inc], PM8611-BIAP Datasheet - Page 202

• Manufacturer Part Number: PM8611-BIAP
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010883, Issue 2
HDR_CRC_ERR
CRC_ERR
OUSER[2:0]
OPAGE[1:0]
RX_LINK[1:0]
RX_STTS_VALID
If this bit is set to a logic one, the last message slot received was received with an errored
CRC-16 field. This bits is updated every message slot. This bit is provided as status only.
If this bit it set to ‘1’, the message at the head of the Receive FIFO has an errored CRC-16
field.
The usual sequence would be to read this register before reading the message buffer to check
if the message buffer that will be read from next has been received with a CRC error. If a
Receive FIFO Synchronization has been started the value of this bit is invalid until the
RX_XFER_SYNC operation has completed. When FAST_RD_EN is a logic one this bit is
valid when RX_FI_BUSY is a logic zero following a Receive FIFO Synchronization. When
FAST_RD_EN is a logic zero the values of RX_FI_BUSY and CRC_ERR change
concurrently and a further read should be made after RX_FI_BUSY is sampled as a logic
zero before checking the value of this bit.
These bits are a reflection of the USER[2:0] bits received in the message header of the latest
received message (without a CRC-16 error) on the Protection Serial Link. OUSER[2] is
output from the SBSLITE on OUSER2 when the Protection Serial Link is selected.
These bits are a reflection of the PAGE[1:0] bits received in the message header of the latest
received message (without a CRC-16 error) on the Protection Serial Link. When the
Protection Serial Link is selected, OPAGE[1] controls the active page of the IMSU and
OPAGE[0] controls the active page of the OMSU.
These bits are a reflection of the LINK[1:0] bits received in the message header of the latest
received message (without a CRC-16 error) on the Protection Serial Link.
This bit indicates that the values of RX_MSG_LVL , RX_LINK, OPAGE, OUSER are valid.
When read with a logic zero this register should be re-read until RX_STTS_VALID is a logic
one. This bit will be cleared for only approximately 0.15% of time.
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
201