PM8611-BIAP PMC [PMC-Sierra, Inc], PM8611-BIAP Datasheet - Page 133

• Manufacturer Part Number: PM8611-BIAP
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010883, Issue 2
RDWRB
BUSY
Four pages are defined for the generator (IADDR [3] = ‘1’) : the configuration page, the
PRBS[22:7] page, the PRBS[6:0] page and the B1/E1 value.
The active high read and active low write (RDWRB) bit selects if the current access to the
internal RAM is an indirect read or an indirect write. Writing to the Indirect Address Register
initiates an access to the internal RAM. When RDWRB is set to logic one, an indirect read
access to the RAM is initiated. The data from the addressed location in the internal RAM
will be transfer to the Indirect Data Register. When RDWRB is set to logic zero, an indirect
write access to the RAM is initiated. The data from the Indirect Data Register will be transfer
to the addressed location in the internal RAM.
The active high RAM busy (BUSY) bit reports if a previously initiated indirect access to the
internal RAM has been completed. BUSY is set to logic one upon writing to the Indirect
Address Register. BUSY is set to logic zero, upon completion of the RAM access. This
register should be polled to determine when new data is available in the Indirect Data
Register.
IADDR[3:0]
0000
0001
0010
0011
0100
0101
IADDR[3:0]
1000
1001
1010
1011
RAM Page
STS-1 path Configuration page
PRBS[22:7] page
PRBS[6:0] page
Reserved
Monitor error count page
Reserved
RAM page
STS-1 path Configuration page
PRBS[22:7] page
PRBS[6:0] page
Reserved
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
132