PM8611-BIAP PMC [PMC-Sierra, Inc], PM8611-BIAP Datasheet - Page 99

• Manufacturer Part Number: PM8611-BIAP
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010883, Issue 2
Register 020H: ISTA Incoming Parity Configuration
Reserved
IPE
INCLIPL
INCLIC1
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The Reserved bits must be set to a logic zero.
The incoming parity interrupt enable bit (IPE) is an active high interrupt enable. When IPE is
set to a logic one, the occurrence of a parity error on the incoming bus will cause an interrupt
to be asserted on the INTB output. When IPE is set to a logic zero, incoming parity errors
will not cause and interrupt.
The INCLIPL bit controls whether the IPL input signal participates in the incoming parity
calculations. When INCLIPL is set to a logic one, the parity signal includes the IPL input.
When INCLIPL is set to a logic zero, parity is calculated without regard to the state of IPL.
These bits only take effect when in TelecomBus mode.
The INCLIC1 bit controls whether the IC1FP input signal participates in the incoming parity
calculations. When INCLIC1 is set to a logic one, the parity signal includes the IC1FP input.
When INCLIC1 is set to a logic zero, parity is calculated without regard to the state of IC1FP.
These bits only take effect when in TelecomBus mode.
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IPE
Reserved
INCLIC1
Reserved
Reserved
Reserved
INCLIPL
Reserved
Reserved
Reserved
Function
Reserved
Reserved
Reserved
Reserved
Reserved
IOP
SBSLITE™ Telecom Standard Product Data Sheet
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Preliminary
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