PM8611-BIAP PMC [PMC-Sierra, Inc], PM8611-BIAP Datasheet - Page 235

• Manufacturer Part Number: PM8611-BIAP
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010883, Issue 2
Register 0E0H: REFDLL Configuration
The REFDLL Configuration Register controls the basic operation of the DLL connected to the
SREFCLK input. This DLL is only used when SREFCLK is operating at 77.76 MHz.
LOCK
ERRORE
Reserved
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 0
The LOCK register is used to force the DLL to ignore phase offsets indicated by the phase
detector after phase lock has been achieved. When LOCK is set to logic zero, the DLL will
track phase offsets measured by the phase detector between the SREFCLK and the DLL’s
reference clock. When LOCK is set to logic one, the DLL will not change the tap after the
phase detector indicates of zero phase offset between the SREFCLK and the reference clock
for the first time.
The ERROR interrupt enable (ERRORE) bit enables the error indication interrupt. When
ERRORE is set high, an interrupt is generated upon assertion event of the ERR output and
ERROR register. When ERRORE is set low, changes in the ERROR and ERR status do not
generate an interrupt.
These bits must be set to set low for correct operation of the SBSLITE.
Type
R/W
R/W
R/W
R/W
R/W
R/W
Reserved
Reserved
ERRORE
Reserved
LOCK
LOCK
Function
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
SBSLITE™ Telecom Standard Product Data Sheet
Default
X
X
X
X
X
X
X
X
X
X
0
0
X
X
0
0
0
Preliminary
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