PM8611-BIAP PMC [PMC-Sierra, Inc], PM8611-BIAP Datasheet - Page 51

Manufacturer Part Number

PM8611-BIAP

Description

Manufacturer

PMC [PMC-Sierra, Inc]

Datasheet

1.PM8611-BIAP.pdf (292 pages)

10.1.11 Fractional Rate Tributary Mapping

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

Document ID: PMC-2010883, Issue 2

ROW

The Fractional Rate SBI mapping is intended for support of data services over fractional DS3 or

similar links. A fractional rate link is mapped into any SPE octet as defined in Table 1. Table 19

shows all the available information (I) octets useable for carrying a Fractional rate link mapped to

a single SPE. There are no V1 to V5 bytes nor frame alignment signals in a fractional rate link.

The Add bus and Drop bus payload signals, IPL and OPL, indicate when a fractional rate

information byte contains valid data or is empty. The fractional rate link Add bus can have the

timing master be either the PHY or the Link Layer device. When the PHY is the timing master the

JUST_REQ signal from the PHY communicates the transmit rate to the Link Layer device. The

JUST_REQ signal is asserted during any of the available fractional rate link octets to indicate that

the PHY can accept another byte of data. For every byte that is marked with the JUST_REQ

signal the Link Layer device should respond with a valid byte to the PHY within a short time. The

PHY accepts data from the Link Layer device whenever it sees valid data as indicated by the IPL

or OPL signal, whether it is timing master or slave.

COL #

1-18

Unused

E1#1,1

#2,1-3,21 E1#1,1

20-81

#2,1-3,21 E1#1,1

83-144

SBSLITE™ Telecom Standard Product Data Sheet

145

#2,1-3,21 E1#1,1

146-207 208

Preliminary

#2,1-3,21

209-270