PM8611-BIAP PMC [PMC-Sierra, Inc], PM8611-BIAP Datasheet - Page 91

• Manufacturer Part Number: PM8611-BIAP
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010883, Issue 2
Register 014H: SBSLITE Master Signal Monitor #1, Accumulation Trigger
This register provides activity monitoring on major SBSLITE inputs. When a monitored input
makes a low to high transition, the corresponding register bit is set high. The bit will remain high
until this register is read, at which point, all the bits in this register are cleared. Bits that depend
on multiple inputs making a low to high transition must have each input make a low to high
transition between subsequent reads before the activity bit will be set high. The corresponding
register bit reading low indicates a lack of transitions. This register should be read periodically to
detect for stuck at conditions.
Writing to this register delimits the accumulation intervals in the various performance monitor
accumulation registers. Counts accumulated in those registers are transferred to holding registers
where they can be read. The counters themselves are then cleared to begin accumulating events
for a new accumulation interval. To prevent loss of data, accumulation intervals must be 1.0
second or shorter. The bits in this register are not affected by write accesses.
Reserved
RC1FPA
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The Reserved bits should be ignored when this register is read.
The RC1FP active bit (RC1FPA) detects low to high transitions on the RC1FP input.
RC1FPA is set high on a rising edge of RC1FP, and is set low when this register is read.
Type
R
R
R
R
R
R
R
R
R
R
R
Reserved
Reserved
Reserved
RC1FPA
SYSCLKA
SREFCLKA
Reserved
Reserved
Reserved
IC1FPA
Function
Unused
Unused
Unused
Unused
Unused
Reserved
SBSLITE™ Telecom Standard Product Data Sheet
Default
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
Preliminary
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