PM8611-BIAP PMC [PMC-Sierra, Inc], PM8611-BIAP Datasheet - Page 241

• Manufacturer Part Number: PM8611-BIAP
• Manufacturer: PMC [PMC-Sierra, Inc]

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Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010883, Issue 2
Test Features Description
The test mode registers, shown in Table 24, are used for production and board testing.
During production testing, the test mode registers are used to apply test vectors. In this case, the
test mode registers (as opposed to the normal mode registers) are selected when A[10] is high.
During board testing, the digital output pins and the data bus are held in a high-impedance state
by simultaneously asserting (low) the CSB, RDB, and WRB inputs. All of the TSBs for the
SBSLITE are placed in test mode 0 so that device inputs may be read and device outputs may be
forced through the microprocessor interface.
Note: The SBSLITE supports a standard IEEE 1149.1 five-signal JTAG boundary scan test port
that can be used for board testing. All digital device inputs may be read and all digital device
outputs may be forced through this JTAG test port.
Table 24 Test Mode Register Memory Map
Master Test and Test Configuration Registers
Notes on Test Mode Register Bits
1. Writing values into unused register bits has no effect. However, to ensure software
2. Writable test mode register bits are not initialized upon reset unless otherwise noted.
compatibility with future, feature-enhanced versions of the product, unused register bits must
be written with logic zero. Reading back unused bits can produce either a logic one or a logic
zero; hence, unused register bits should be masked off by software when read.
Address
000H-0FFH
100H
101H - 1FFH
Register
Normal Mode Registers
Master Test Register
Reserved For Test
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
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