PM8611-BIAP PMC [PMC-Sierra, Inc], PM8611-BIAP Datasheet - Page 194

• Manufacturer Part Number: PM8611-BIAP
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010883, Issue 2
Register 0A5H: PILC Transmit Status and FIFO Synch Register
TX_XFER_SYNC
TX_FI_BUSY
TX_MSG_LVL[3:0]
Bit
Bit 15
Bit 14:13
Bit 12:11
Bit 10:8
Bit 7:6
Bit 5:2
Bit 1
Bit 0
Writing ‘1’ to this bit initializes the next write sequence to be to the beginning of the next
message. After a ‘1’ had been written successive writes to the Transmit FIFO will be to
location zero of the next available slot. If a partial message has been written,
TX_XFER_SYNC indicates that the current message is complete and that subsequent writes
will be to the next message. If more than 32 bytes are written, the 33rd byte will be the first
byte of the next message. The purpose of this bit is to unambiguously align the message
boundaries. Another use would be to abandon the current write and move the write pointer to
the beginning of the next message. (Previous message data will remain in the unwritten
portion of the message being abandoned, which will have to be ignored by the receiving
software).
If the message FIFO pointers are already at a message boundary then writing this bit to a ‘1’
will have no affect.
On reads this bit is always returned as a ‘0’.
This bit indicates that the internal hardware is transferring the data from the Transmit FIFO
registers (TDAT) into the internal RAM. This bit need not be read by software if the time
interval between successive 32 bit transfers is greater than 3 SYSCLK cycles.
This indicates the current number of messages in the TXFIFO.
TX_MSG_LVL[3:0]
0000
:
1000
Type
R
R
R
R
R
R
R
W
TX_MSG_LVL_VALID
IPAGE[1:0]
IUSER[2:0]
TX_FI_BUSY
TX_XFER_SYNC
Function
TX_LINK[1:0]
Unused
TX_MSG_LVL[3:0]
Number of Messages
0
:
8
SBSLITE™ Telecom Standard Product Data Sheet
Default
X
00
XX
X00
00
0000
0
0
Preliminary
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