PM8611-BIAP PMC [PMC-Sierra, Inc], PM8611-BIAP Datasheet - Page 190

• Manufacturer Part Number: PM8611-BIAP
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010883, Issue 2
Register 09FH: WILC Interrupt Reason Register
This register contains the status of events that may be enabled to generate interrupts..
All bits in this register are cleared on read.
OUSER0_CHGI
OPAGE_CHGI[1:0]
RX_LINK_CHGI
RX_OVFLWI
RX_THRSHLDI
RX_TIMEOUTI
Bit
Bit 15:7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2:1
Bit 0
A logic one in this bit indicates that the last received value of the OUSER[0] header bit has
changed from a ‘0’ to a ‘1’ from the previously received values. This bit is cleared on a read.
A logic one in these bits indicates that the last received value of the corresponding
OPAGE[1:0] header bits has changed from the previously received values. These bits are
cleared on read.
A logic one in this bit indicates that the last received value of the LINK[1:0] header bits has
changed from the previously received values. This bit is cleared on a read.
A logic one in this bit indicates that a Receive FIFO Overflow has occurred. This bit is
cleared on a read.
A logic one in this bit indicates that the Receive FIFO Threshold has been reached. This bit is
cleared on a read.
A logic one in this bit indicates a Receive FIFO Timeout. This bit is cleared on read.
Type
R
R
R
R
R
R
R
RX_TIMEOUTI
RX_THRSHLDI
RX_OVFLWI
RX_LINK_CHGI
OPAGE_CHGI[1:0]
OUSER0_CHGI
Function
Unused
SBSLITE™ Telecom Standard Product Data Sheet
Default
0
0
0
0
0
00
0
Preliminary
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