PM8611-BIAP PMC [PMC-Sierra, Inc], PM8611-BIAP Datasheet - Page 282

• Manufacturer Part Number: PM8611-BIAP
• Manufacturer: PMC [PMC-Sierra, Inc]

17
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010883, Issue 2
Symbol
tS
tH
tS
tH
tV
tS
tH
tP
tZ
tZ
Microprocessor Interface Timing Characteristics
(T C = -40 °C to +85 °C, V DDO = 3.3 V ± 8%, V DDI = 1.8 V ± 5%)
Table 30 Microprocessor Interface Read Access (Figure 39)
Figure 39 Microprocessor Interface Read Timing
Notes on Microprocessor Interface Read Timing
1.
2.
3.
RD
INTH
AR
AR
ALR
ALR
L
LR
LR
RD
(CSB+RDB)
Output propagation delay time is the time in nanoseconds from the 1.4 V point of the reference signal to
the 1.4 V point of the output.
Maximum output propagation delays are measured with a 100 pF load on the Microprocessor Interface
data bus, (D[15:0]).
A valid read cycle is defined as a logical OR of the CSB and the RDB signals.
D[7:0]
A[11:0]
INTB
ALE
Parameter
Address to Valid Read Set-up Time
Address to Valid Read Hold Time
Address to Latch Set-up Time
Address to Latch Hold Time
Valid Latch Pulse Width
Latch to Read Set-up
Latch to Read Hold
Valid Read to Valid Data Propagation Delay
Valid Read Negated to Output Tri-state
Valid Read Negated to INTB High
tSalr
tVl
tVl
tSar
tSlr
tPrd
SBSLITE™ Telecom Standard Product Data Sheet
tHalr
VALID
tZrd
tHar
tZinth
Min
5
5
5
5
2
0
5
tHlr
Max
15
15
20
Preliminary
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
281