PM8611-BIAP PMC [PMC-Sierra, Inc], PM8611-BIAP Datasheet - Page 185

• Manufacturer Part Number: PM8611-BIAP
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010883, Issue 2
Register 09BH: WILC Receive Status and FIFO Synch Register
When this register is read, it returns the status for the Receive Message Channel. When a logic
one is written into bit 0 of this register, it is used to synchronize the Receive FIFO to the start of a
message boundary or perform a message skip.
RX_XFER_SYNC
Bit
Bit 15
Bit 14:13
Bit 12:11
Bit 10:8
Bit 7
Bit 6
Bit 5:2
Bit 1
Bit 0
Bit 0
Writing a logic one to this bit initiates a read sequence from the start of the next unread
message. The hardware aligns the message read buffer address to the start of the next unread
message and prefetches the first Dword from the unread message buffer so that it is ready to
be read from the WILC Receive FIFO Data registers.
An unread message in this context means that the s/w has not read any of the message
payload data by reading the WILC Receive FIFO Data registers.
After the RX XFER SYNC process has been completed successive reads from the Receive
FIFO return the last Dword read from the Receive FIFO and prefetch the next Dword (when
available).
This bit must be written to a logic one at the start of a message read sequence.
When multiple complete messages are being read (software knows that there is more than one
message in the FIFO using the RX_MSG_LVL bits) this bit does not need to be written
between individual message reads. It must be written for the 1
When software uses a variable length message protocol it may want to abandon reading a
message buffer before reading the entire message buffer of 8 DWords (16 Words). In this case
this bit must be written with a ‘1’ to move the message pointer to the start of the next message
buffer before starting the read of that buffer.
After writing this bit with a logic one software should not start reading the FIFO until the
RX_FI_BUSY bit has cleared.
Type
R
R
R
R
R
R
R
R
R
W
RX_STTS_VALID
OPAGE[1:0]
OUSER[2:0]
CRC_ERR
HDR_CRC_ERR
RX_FI_BUSY
RX_SYNC_DONE
RX_XFER_SYNC
Function
RX_LINK[1:0]
RX_MSG_LVL[3:0]
SBSLITE™ Telecom Standard Product Data Sheet
st
message.
Default
X
00
00
000
0
0
0000
0
X
0
Preliminary
184