PM8611-BIAP PMC [PMC-Sierra, Inc], PM8611-BIAP Datasheet - Page 198

• Manufacturer Part Number: PM8611-BIAP
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010883, Issue 2
Register 0A9H: PILC Receive FIFO Control Register
RX_BYPASS
RX_CRC_SWIZ_EN
FAST_RD_EN
Bit
Bit 15:3
Bit 2
Bit 1
Bit 0
When this bit is set to a logic one. The PILC’s message receive functions are bypassed and no
messages are extracted from the Receive Working Serial Link. The receive message FIFO
RAM is disabled and thus message data reads will return undefined data.
When this bit is set to a logic one, the calculated CRC-16 is bit reversed before being
compared with CRC-16 bytes of the received message. This facility can be used for
diagnostic testing of CRC-16 generation and checking functionality
When this bit is set to ‘1’, the time to read the Receive FIFO is reduced by 1 SYSCLK cycle.
For receive FIFO reads induced by writing the RX_XFER_SYNC bit to a ‘1’ the time for the
completion of the receive FIFO read is reduced from approximately 5 SYSCLK cycles when
FAST_RD_EN = ‘0’ to approximately 4 SYSCLK cycles when FAST_RD_EN = ‘1’.
For receive FIFO reads induced by reading from the Receive FIFO Data register Low the
time for the completion of the receive FIFO read is reduced from approximately 4 SYSCLK
cycles when FAST_RD_EN = ‘0’ to approximately 3 SYSCLK cycles when FAST_RD_EN =
‘1’.
Type
R
R/W
R/W
R/W
FAST_RD_EN
RX_CRC_SWIZ_EN
RX_BYPASS
Function
Unused
SBSLITE™ Telecom Standard Product Data Sheet
Default
0
0
0
0
Preliminary
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