PM8611-BIAP PMC [PMC-Sierra, Inc], PM8611-BIAP Datasheet - Page 242

• Manufacturer Part Number: PM8611-BIAP
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010883, Issue 2
Register 100H: Master Test
This register is used to enable SBSLITE test features. All bits, except PMCTST and PMCATST
are reset to zero by a reset of the SBSLITE using either the RSTB input. PMCTST is reset when
CSB is logic one. PMCATST is reset when both CSB is high and RSTB is low. PMCTST and
PMCATST can also be reset by writing a logic zero to the corresponding register bit.
HIZIO, HIZDATA
IOTST
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The HIZIO and HIZDATA bits control the tri-state modes of the SBSLITE. While the HIZIO
bit is a logic one, all output pins of the SBSLITE except the data bus and output TDO are
held tri-state. The microprocessor interface is still active. While the HIZDATA bit is a logic
one, the data bus is also held in a high-impedance state which inhibits microprocessor read
cycles. The HIZDATA bit is overridden by the DBCTRL bit.
The IOTST bit is used to allow normal microprocessor access to the test registers and control
the test mode in each TSB block in the SBSLITE for board level testing. When IOTST is a
logic one, all blocks are held in test mode and the microprocessor may write to a block’s test
mode 0 registers to manipulate the outputs of the block and consequently the device outputs.
Type
R/W
R/W
W
W
R/W
W
R/W
Reserved
PMCATST
PMCTST
DBCTRL
HIZDATA
HIZIO
Function
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
IOTST
SBSLITE™ Telecom Standard Product Data Sheet
Default
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
Preliminary
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