PM8611-BIAP PMC [PMC-Sierra, Inc], PM8611-BIAP Datasheet - Page 186

• Manufacturer Part Number: PM8611-BIAP
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010883, Issue 2
RX_SYNC_DONE
RX_FI_BUSY
RX_MSG_LVL[3:0]
In the worst case this will take 5 SYSCLK cycles when FAST_RD_EN = ‘1’ and 4 SYSCLK
cycles when FAST_RD_EN = ‘0’.
At this point the 1
valid. Software may abandon a CRC errored message without reading the message buffer by
writing this bit with a logic one again.
On reads this bit is always returns the RX_SYNC_DONE status.
This bit indicates the status of an RX_XFER_SYNC operation. When this bit is a logic one it
indicates that an RX_XFER_SYNC has been done. S/W should check this bit at the start of a
message read sequence or when attempting to perform a message skip sequence.
This bit indicates that the internal hardware is transferring data from the Receive FIFO RAM
into the Receive FIFO registers. The bit is set following a write to this register with the
RX_XFER_SYNC bit set or following a read from the WILC Receive FIFO Data Low
register.
Following an RX_XFER_SYNC write this bit need not be read by software if
the time interval to the successive Receive FIFO DATA register read is greater than
approximately 5 SYSCLK cycles when FAST_RD_EN = ‘1’ or approximately 4 SYSCLK
cycles when FAST_RD_EN = ‘0’.
This bit need not be read by software if the time interval between successive Receive FIFO
DATA register reads greater than approximately 4 SYSCLK cycles when FAST_RD_EN =
‘1’ or approximately 3 SYSCLK cycles when FAST_RD_EN = ‘0’.
This means between a read access from the WILC Received FIFO Data Low register and a
read from the WILC Received FIFO Data High register. Note that there is no time restriction
between a read accesses from the WILC Received FIFO Data High register and a read from
the WILC Received FIFO Data Low register
This indicates the current number of messages in the Receive FIFO.
Values greater than 1000 will not occur.
RX_MSG_LVL[3:0]
0000
:
1000
st
DWORD of the message is available for reading and the CRC_ERR bit is
Number of Messages
0
:
8
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
185