PM8611-BIAP PMC [PMC-Sierra, Inc], PM8611-BIAP Datasheet - Page 28

• Manufacturer Part Number: PM8611-BIAP
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010883, Issue 2
Pin Name
Microprocessor Interface (30 Signals)
CSB
RDB
WRB
D[15]
D[14]
D[13]
D[12]
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
A[8]/TRS
A[7]
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
ALE
Type
Input
Input
Input
I/O
Input
Input
Pin
No.
M2
M1
M3
L4
N5
N6
P6
M6
L6
N7
M8
N8
L9
P10
M10
N10
L10
P11
M11
N11
P12
M12
N13
N14
M13
M14
L14
L11
L2
Function
Chip Select Bar. The active low chip select signal (CSB) controls
microprocessor access to registers in the SBSLITE device. CSB is
set low during SBSLITE Microprocessor Interface Port register
accesses. CSB is set high to disable microprocessor accesses.
If CSB is not required (i.e. register accesses controlled using RDB
and WRB signals only), CSB should be connected to an inverted
version of the RSTB input.
Read Enable Bar. The active low read enable bar signal (RDB)
controls microprocessor read accesses to registers in the SBSLITE
device. RDB is set low and CSB is also set low during SBSLITE
Microprocessor Interface Port register read accesses. The
SBSLITE drives the D[15:0] bus with the contents of the addressed
register while RDB and CSB are low.
Write Enable Bar. The active low write enable bar signal (WRB)
controls microprocessor write accesses to registers in the SBSLITE
device. WRB is set low and CSB is also set low during SBSLITE
Microprocessor Interface Port register write accesses. The
contents of D[15:0] are clocked into the addressed register on the
rising edge of WRB while CSB is low.
Microprocessor Data Bus. The bi-directional data bus, D[15:0] is
used during SBSLITE Microprocessor Interface Port register reads
and write accesses. D[15] is the most significant bit of the data
words and D[0] is the least significant bit.
Microprocessor Address Bus. The microprocessor address bus
(A[8:0]) selects specific Microprocessor Interface Port registers
during SBSLITE register accesses.
A[8] is also the Test Register Select (TRS) address pin and selects
between normal and test mode register accesses. TRS is set high
during test mode register accesses, and is set low during normal
mode register accesses.
Address Latch Enable. The address latch enable signal (ALE) is
active high and latches the address bus (A[11:0]) when it is set low.
The internal address latches are transparent when ALE is set high.
ALE allows the SBSLITE to interface to a multiplexed address/data
bus. ALE has an integral pull up resistor.
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
27