PM8611-BIAP PMC [PMC-Sierra, Inc], PM8611-BIAP Datasheet - Page 37

• Manufacturer Part Number: PM8611-BIAP
• Manufacturer: PMC [PMC-Sierra, Inc]

10.1.2
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010883, Issue 2
Table 3 E1/TVT2 Tributary Column Numbering
SBI Timing Master Modes
The SBI is a synchronous bus which is timed to a reference 19.44 MHz clock and a 2 KHz frame
pulse (8 KHz is easily derived from the 2 KHz and 19.44 MHz clock). All sources and sinks of
data on this bus are timed to the reference clock and frame pulse.
The data format on the data bus allows for compensating between clock differences on the PHY,
SBI and Link Layer devices. This is achieved by floating data structures within the SBI format.
Timing is communicated across the SBI bus by floating data structures within the bus. Payload
indicator signals in the SBI control the position of the floating data structure and therefore the
timing. When sources are running faster than the SBI the floating payload structure is advanced
by an octet be passing an extra octet in the V3 octet locations (H3 octet for DS3 and E3
mappings). When the source is slower than the SBI the floating payload is retarded by leaving the
octet after the V3 or H3 octet unused. Both these rate adjustments are indicated by the SBI
control signals.
On the Drop bus, all timing is sourced from the PHY and is passed onto the Link Layer device by
the arrival rate of data over the SBI.
On the Add bus, timing can be controlled by either the PHY or the Link Layer device by
controlling the payload and by making justification requests. When the Link Layer device is the
timing master the PHY device gets its transmit timing information from the arrival rate of data
across the SBI. When the PHY device is the timing master it signals the Link Layer device to
speed up or slow down with justification request signals. The PHY timing master indicates a
speedup request to the Link Layer by asserting the justification request signal high during the V3
or H3 octet. When this is detected by the Link Layer it will advance the channel by inserting data
in the next V3 or H3 octet as described above. The PHY timing master indicates a slowdown
request to the Link Layer by asserting the justification request signal high during the octet after
the V3 or H3 octet. When detected by the Link Layer it will retard the channel by leaving the
octet following the next V3 or H3 octet unused. Both advance and retard rate adjustments take
place in the frame or multi-frame following the justification request.
E1#
1,1
2,1
3,1
1,2
2,2
1,21
2,21
3,21
SPE1 Column
7,28,49,70
8,29,50,71
27,48,69,90
7,28,49,70
8,29,50,71
27,48,69,90
SPE2 Column
SBSLITE™ Telecom Standard Product Data Sheet
SPE3 Column
7,28,49,70
27,48,69,90
SBI Column
19,82,145,208
20,83,146,209
21,84,147,210
22,85,148,211
23,86,149,212
79,142,205,268
80,143,206,269
81,144,207,270
Preliminary
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