PM8611-BIAP PMC [PMC-Sierra, Inc], PM8611-BIAP Datasheet - Page 60

• Manufacturer Part Number: PM8611-BIAP
• Manufacturer: PMC [PMC-Sierra, Inc]

10.13 LVDS Receivers
10.14 Data Recovery Units
10.15 Receive 8B/10B Decoders
10.15.1 FIFO Buffer
10.15.2 Serial SBI336S and TelecomBus Alignment
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010883, Issue 2
The LVDS Receivers, RWLV and RPLV, convert LVDS signaling levels to 8B/10B encoded
digital bit-serial. The Receive Working LVDS Interface block, RWLV, connects to the working
receive LVDS links, RPWRK/RNWRK. The Receive Protect LVDS Interface block, RPLV,
connects to the protect receive LVDS link RPPROT/RNPROT.
The Data Recovery Units, WDRU and PDRU, monitor the receive LVDS link for transitions to
determine the extent of bit cycles on the link. It then adjusts its internal timing to sample the link
in the middle of the data “eye”. WDRU retrieves data from the working receive LVDS link,
RPWRK/RNWRK. PDRU processes the protect receive LVDS link, RPPROT/RNPROT.
The DRU block also converts the serial stream into 10-bit words. The words are constructed
from ten consecutive received bits without regard to 8B/10B character boundaries.
The Receive 8B/10B serial SBI336S Bus decoders, RW8D and RP8D, frame to the receive
stream to find 8B/10B character boundaries. It also contains a FIFO to bridge between the timing
domain of the receive LVDS links and the system clock timing domain. The RW8D block
performs framing and elastic store functions on data retrieved from the working receive LVDS
link, RPWRK/RNWRK. The RP8D block processes data on the protect receive LVDS link,
RPPROT/RNPROT.
The FIFO buffer sub-block provides isolation between the timing domain of the associated
receive LVDS link and that of the system clock, SYSCLK. The FIFO also provides a retiming
function to allow individual links in a multi-SBS system to have varying interconnect delay. This
eases timing distribution and synchronization in large systems. Data with arbitrary alignment to
8B/10B characters are written into a 10-bit by 24-word deep FIFO at the link clock rate. Data is
read from the FIFO at every SYSCLK cycle.
The alignment functionality preformed by each receiver can be broken down into two parts,
character alignment and frame alignment. Character alignment finds the 8B/10B character
boundary in the arbitrarily aligned incoming data. Frame alignment finds SBI336S or
TelecomBus frame and multiframe boundaries within the Serial link.
The character and frame alignment are expected to be robust enough for operation over a cabled
interconnect.
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
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