PM8611-BIAP PMC [PMC-Sierra, Inc], PM8611-BIAP Datasheet - Page 273

• Manufacturer Part Number: PM8611-BIAP
• Manufacturer: PMC [PMC-Sierra, Inc]

14.1
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Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010883, Issue 2
Functional Timing
Incoming SBI336 Bus Functional Timing
Figure 31 shows the functional timing for the incoming 77.76 MHz SBI336 bus configured for
connection to a physical layer device. When configured for the SBI336 bus, timing is provided
by a 77.76 MHz SREFCLK which is also connected to SYSCLK. When connecting to a physical
layer device, the justification request signal, JUST_REQ, is used by the physical layer device to
control link timing from a slave link layer device and is an input to the SBSLITE.
Figure 31 shows a number of capabilities of the SBI bus. IC1FP is a 2 KHz pulse that indicates
the SBI336 frame alignment from which all control signals and data are synchronized. The
payload signal indicates valid tributary data as well as positive and negative tributary timing
adjustments. In Figure 31 the first occurrence of IPL high shows a negative timing adjustment
where valid data is carried in the V3 location. The last cycle with IPL low indicates a positive
timing adjustment in the tributary octet after V3 where there is no valid data. The IV5 signal
indicates that the current data octet is the V5 octet used for tributary framing alignment. The
JUST_REQ signal is only valid during the V3 octets and the tributary octets following the V3
octets. The first occurrence of JUST_REQ high during the V3 octet indicates to the slave link
layer device that it should speed next frame by performing a negative timing adjustment. The
second occurrence of JUST_REQ high during the tributary octet after the V3 octet indicates to
the slave link layer device that it should slow down by performing a positive timing adjustment
during the next frame. The last V3 in the diagram is meant to be the last V3 for all the tributaries.
The ICMP signal selects the active connection memory page in the memory switch. It is sampled
at the C1 byte position in every multiframe. ICMP is ignored at all other positions within the SBI
frame. The connection memory page is switched on the next SBI bus multiframe boundary after
ICMP is sampled. The SBI multiframe can be either 4 or 48 frames, depending on the value of
MF_48 in the SBSLITE Master Configuration Register.
Figure 31 Incoming SBI336 Functional Timing
JUST_REQ
SREFCLK
IDATA[7:0]
IC1FP
ICMP
IDP
IPL
IV5
valid
C1
V3
V3
SBSLITE™ Telecom Standard Product Data Sheet
DS0#9 V3
DS0#4 V5
DS0#2DS0#7
Preliminary
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