S912XET512J3VALR Freescale Semiconductor, S912XET512J3VALR Datasheet

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MC9S12XEP100 Reference Manual Covers MC9S12XE Family HCS12X Microcontrollers MC9S12XEP100RMV1 Rev. 1.25 02/2013 freescale.com ...

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To provide the most up-to-date information, the document revision on the World Wide Web is the most current. A printed copy may be an earlier revision. To verif, refer to: freescale.com This document contains information for the complete S12XE-Family and ...

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... Serial Communication Interface (S12SCIV5 723 Chapter 21 Serial Peripheral Interface (S12SPIV5 761 Chapter 22 Timer Module (TIM16B8CV2) Block Description . . . . . . . . . . 787 Chapter 23 Voltage Regulator (S12VREGL3V3V1 815 Chapter 24 128 KByte Flash Module (S12XFTM128K2V1 832 Chapter 25 256 KByte Flash Module (S12XFTM256K2V1 891 Freescale Semiconductor MC9S12XE-Family Reference Manual Rev. 1.25 3 ...

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... KByte Flash Module (S12XFTM768K4V2 1077 Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2 1140 Appendix A Electrical Characteristics 1201 Appendix B Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1258 Appendix C PCB Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1260 Appendix D Derivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1268 Appendix E Detailed Register Address Map 1271 Appendix F Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1322 4 MC9S12XE-Family Reference Manual Rev. 1.25 Freescale Semiconductor ...

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... Blank Page 6 MC9S12XE-Family Reference Manual Rev. 1.25 Freescale Semiconductor ...

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... ADC0 Channel[17] Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 1.8 ADC1 External Trigger Input Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 1.9 MPU Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 1.10 VREG Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 1.10.1 Temperature Sensor Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 1.11 BDM Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 1.12 S12XEPIM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 1.13 Oscillator Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Port Integration Module (S12XEPIMV1) 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Freescale Semiconductor Chapter 1 Chapter 2 MC9S12XE-Family Reference Manual Rev. 1.25 7 ...

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... Port S Wired-Or Mode Register (WOMS 129 2.3.36 PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 2.3.37 Port M Data Register (PTM 130 2.3.38 Port M Input Register (PTIM 131 2.3.39 Port M Data Direction Register (DDRM 132 2.3.40 Port M Reduced Drive Register (RDRM 134 2.3.41 Port M Pull Device Enable Register (PERM 134 8 MC9S12XE-Family Reference Manual Rev. 1.25 Freescale Semiconductor ...

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... Port AD1 Reduced Drive Register 0 (RDR0AD1 162 2.3.82 Port AD1 Reduced Drive Register 1 (RDR1AD1 162 2.3.83 Port AD1 Pull Up Enable Register 0 (PER0AD1 163 2.3.84 Port AD1 Pull Up Enable Register 1 (PER1AD1 163 2.3.85 Port R Data Register (PTR 164 2.3.86 Port R Input Register (PTIR 164 Freescale Semiconductor MC9S12XE-Family Reference Manual Rev. 1.25 9 ...

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... S12X Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 3.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 3.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 3.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 3.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 3.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 3.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 3.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 3.4.1 MCU Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 3.4.2 Memory Map Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 10 Chapter 3 MC9S12XE-Family Reference Manual Rev. 1.25 Freescale Semiconductor ...

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... Internal Visibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 5.4.3 Accesses to Port Replacement Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 5.4.4 Stretched External Bus Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 5.4.5 Data Select and Data Direction Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 5.4.6 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 5.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 5.5.1 Normal Expanded Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 5.5.2 Emulation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Freescale Semiconductor Chapter 4 Chapter 5 MC9S12XE-Family Reference Manual Rev. 1.25 11 ...

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... Standard BDM Firmware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 7.4.5 BDM Command Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 7.4.6 BDM Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 7.4.7 Serial Interface Hardware Handshake Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 7.4.8 Hardware Handshake Abort Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 7.4.9 SYNC — Request Timed Reference Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 12 Chapter 6 Interrupt (S12XINTV2) Chapter 7 MC9S12XE-Family Reference Manual Rev. 1.25 Freescale Semiconductor ...

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... Complete Memory Erase (Special Modes 351 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 10.1.1 Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 10.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 10.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 10.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 10.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 10.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 Freescale Semiconductor Chapter 8 Chapter 9 Security (S12XE9SECV2) Chapter 10 XGATE (S12XGATEV3) MC9S12XE-Family Reference Manual Rev. 1.25 13 ...

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... Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 11.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 11.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 11.4.1 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 11.4.2 Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 11.4.3 Low Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 11.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 11.5.1 Description of Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 11.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 14 Chapter 471 MC9S12XE-Family Reference Manual Rev. 1.25 Freescale Semiconductor ...

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... Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 14.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 14.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 14.2.1 IOC7 — Input Capture and Output Compare Channel 529 14.2.2 IOC6 — Input Capture and Output Compare Channel 529 Freescale Semiconductor Chapter 12 — Operating and Ground Voltage Pins . . . . . . . . . . . . . . . . . . . . 500 Chapter 13 Chapter 14 MC9S12XE-Family Reference Manual Rev. 1.25 ...

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... IIC Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599 Freescale’s Scalable Controller Area Network (S12MSCANV3) 16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605 16.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606 16.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606 16.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 16.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 16.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608 16.2.1 RXCAN — CAN Receiver Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608 16 Chapter 15 Chapter 16 MC9S12XE-Family Reference Manual Rev. 1.25 Freescale Semiconductor ...

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... Interrupt Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673 17.4.3 Hardware Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673 17.5 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674 17.5.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674 17.5.2 Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674 17.5.3 Flag Clearing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674 17.6 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674 Periodic Interrupt Timer (S12PIT24B4CV2) 18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677 18.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677 18.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677 18.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677 18.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678 Freescale Semiconductor Chapter 17 Chapter 18 MC9S12XE-Family Reference Manual Rev. 1.25 17 ...

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... Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709 19.4.1 PWM Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709 19.4.2 PWM Channel Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712 19.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720 19.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721 Serial Communication Interface (S12SCIV5) 20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723 20.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723 20.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724 20.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724 20.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725 20.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726 18 Chapter 19 Chapter 20 MC9S12XE-Family Reference Manual Rev. 1.25 Freescale Semiconductor ...

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... Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764 21.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765 21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773 21.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774 21.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775 21.4.3 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776 21.4.4 SPI Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781 21.4.5 Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782 21.4.6 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783 21.4.7 Low Power Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784 Freescale Semiconductor Chapter 21 MC9S12XE-Family Reference Manual Rev. 1.25 19 ...

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... VDDA, VSSA — Regulator Reference Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 818 23.2.3 VDD, VSS — Regulator Output1 (Core Logic) Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 818 23.2.4 VDDF — Regulator Output2 (NVM Logic) Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819 23.2.5 VDDPLL, VSSPLL — Regulator Output3 (PLL) Pins . . . . . . . . . . . . . . . . . . . . . . . . . 819 20 Chapter 22 Chapter 23 MC9S12XE-Family Reference Manual Rev. 1.25 Freescale Semiconductor ...

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... Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889 24.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 890 24.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . . 890 24.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890 256 KByte Flash Module (S12XFTM256K2V1) 25.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891 Freescale Semiconductor Chapter 24 Chapter 25 MC9S12XE-Family Reference Manual Rev. 1.25 21 ...

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... Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013 26.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . 1014 26.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . 1014 26.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1014 512 KByte Flash Module (S12XFTM512K3V1) 27.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016 22 Chapter 26 Chapter 27 MC9S12XE-Family Reference Manual Rev. 1.25 Freescale Semiconductor ...

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... Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . 1137 28.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . 1138 28.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . 1138 28.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1138 1024 KByte Flash Module (S12XFTM1024K5V2) 29.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1140 Freescale Semiconductor Chapter 28 Chapter 29 MC9S12XE-Family Reference Manual Rev. 1.25 23 ...

Page 24

... A.3 NVM, Flash and Emulated EEPROM 1224 A.3.1 Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1224 A.3.2 NVM Reliability Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1231 A.4 Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1234 A.5 Output Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1235 A.5.1 Resistive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1235 A.5.2 Capacitive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1235 A.5.3 Chip Power-up and Voltage Drops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1235 A.6 Reset, Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1236 24 Appendix A Electrical Characteristics MC9S12XE-Family Reference Manual Rev. 1.25 Freescale Semiconductor ...

Page 25

... A.7.3 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1247 B.1 208 MAPBGA 1259 B.2 144-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1259 B.3 112-Pin LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1261 B.4 80-Pin QFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1262 D.1 Memory Sizes and Package Options S12XE - Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1268 D.2 Pinout explanations 1270 Freescale Semiconductor Appendix B Package Information Appendix C PCB Layout Guidelines Appendix D Derivative Differences ...

Page 26

... MC9S12XE-Family Reference Manual Rev. 1.25 Freescale Semiconductor ...

Page 27

... Pin MAPBGA, 144-Pin LQFP, 112-Pin LQFP or 80-Pin QFP options. 1.1.1 Features Features of the MC9S12XE-Family are listed here. Please see Table D-2.for memory options and Table D- 2. for the peripheral features that are available on the different family members. Freescale Semiconductor MC9S12XE-Family Reference Manual Rev. 1.25 27 ...

Page 28

... Low power loop control Pierce oscillator utilizing a 4MHz to 16MHz crystal — Good noise immunity — Full-swing Pierce option utilizing a 2MHz to 40MHz crystal — Transconductance sized for optimum start-up margin for typical crystals • IPLL (Internally filtered, frequency modulated phase-locked-loop clock generation) 28 MC9S12XE-Family Reference Manual Rev. 1.25 Freescale Semiconductor ...

Page 29

... Internal oscillator for conversion in Stop modes — Wake from low power modes on analog comparison > or <= match • Five MSCAN (1 M bit per second, CAN 2 software compatible modules) — Five receive and three transmit buffers Freescale Semiconductor MC9S12XE-Family Reference Manual Rev. 1.25 Chapter 1 Device Overview MC9S12XE-Family 29 ...

Page 30

... On-Chip Voltage Regulator — Two parallel, linear voltage regulators with bandgap reference — Low-voltage detect (LVD) with low-voltage interrupt (LVI) — Power-on reset (POR) circuit — 3.3V and 5V range operation — Low-voltage reset (LVR bus clock cycles MC9S12XE-Family Reference Manual Rev. 1.25 Freescale Semiconductor ...

Page 31

... Low-power modes: • System stop modes — Pseudo stop mode — Full stop mode with fast wake-up option • System wait mode Operating system states • Supervisor state • User state Freescale Semiconductor MC9S12XE-Family Reference Manual Rev. 1.25 Chapter 1 Device Overview MC9S12XE-Family 31 ...

Page 32

... RXD Asynchronous Serial IF TXD SCI7 RXD Asynchronous Serial IF TXD SCI2 RXD Asynchronous Serial IF TXD IIC1 SDA Inter IC Module SCL CAN4 RXCAN msCAN 2.0B TXCAN Freescale Semiconductor PAD[15:0] PAD[31:16] PT[7:0] PR[7:0] PP[7:0] PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PH0 PH1 PH2 PH3 PH4 PH5 ...

Page 33

... Freescale Semiconductor Table 1-1. Device Register Memory Map Module ) PIM (port integration module MMC (memory map control) PIM (port integration module) EBI (external bus interface) MMC (memory map control) ...

Page 34

... SCI6 (serial communications interface) SCI7 (serial communications interface) PIT (periodic interrupt timer) PIM (port integration module) XGATE Reserved TIM (timer module) Reserved NOTE Table 1-1 is not allocated to any module. MC9S12XE-Family Reference Manual Rev. 1.25 Size (Bytes 1024 Freescale Semiconductor ...

Page 35

... NOTE: On smaller derivatives the flash memory map is split into 2 ranges separated by an unimplemeted range, as depicted by the dashed lines. For more information refer to tables below and MMC section. Figure 1-2. MC9S12XE100 Global Memory Map Freescale Semiconductor 0x00_0000 0x00_07FF RAM_LOW 0x0F_FFFF EPAGE RPAGE ...

Page 36

... RAM access range. 36 EE_LOW Flash Blocks 0x13_F000 B3, B2, B1S, B1N, B0 0x13_F000 B3, B2, B1S, B1N, B0 0x13_F000 B1N, B1S, B0 0x13_F000 B1S, B0(128K) Table 1-4. Within EEPROM resource range an address range exists MC9S12XE-Family Reference Manual Rev. 1.25 Registers Freescale Semiconductor ...

Page 37

... The 128K memory map is split into a 64K block from 0x78_0000 to 0x78_FFFF and a 64K block from 0x7F_0000 to 0x7F_FFFF Table 1-5. Derivative Dependent Flash Block Mapping Device 0x70_0000 9S12XEP100 B3 9S12XEP768 — 9S12XEQ512 — 9S12XEx384 — Freescale Semiconductor Table 1-3. XGATE Resources XGRAM_LOW = 0x0F_8000 (1) XGFLASH_HIGH = 0x78_8000 PPAGE RAM_LOW (1) 64 0x0F_0000 48 0x0F_4000 32 ...

Page 38

... The block reduced size 128K block on the 256K derivative. On the larger derivatives 256K block. The block reduced size 64K block on the 128K derivative. 38 0x74_0000 0x78_0000 0x7A_0000 — B1S B1S (64K) — MC9S12XE-Family Reference Manual Rev. 1.25 0x7C_0000 0x7E_0000 — — B0(128K) — — B0 (64K) Freescale Semiconductor ...

Page 39

... XGATE Local Memory Map 0x0000 Registers 0x0800 FLASH RAM 0xFFFF Freescale Semiconductor XGRAM_LOW XGFLASH_HIGH Figure 1-3. XGATE Global Address Mapping MC9S12XE-Family Reference Manual Rev. 1.25 Chapter 1 Device Overview MC9S12XE-Family Global Memory Map 0x00_0000 Registers 0x00_07FF RAM 0x0F_FFFF 0x78_0800 FLASH 0x7F_FFFF 39 ...

Page 40

... The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses 0x001A and 0x001B). The read-only value is a unique part ID for each revision of the chip. number and Mask Set number. 40 MC9S12XE-Family Reference Manual Rev. 1.25 Table 1-6 shows the assigned part ID Freescale Semiconductor ...

Page 41

... Bit 5-4: Major mask set revision number including FAB transfers Bit 3-0: Minor — non full — mask set revision 2. Currently available as MC9S12XEP100 die only 3. Currently available as MC9S12XEQ512 die only 4. Currently available as MC9S12XET256 die only 1.2 Signal Description Freescale Semiconductor Table 1-6. Assigned Part ID Numbers Mask Set Number 0M22E 1M22E 2M22E 0M48H ...

Page 42

... LQFP package with an external bus interface (address/data bus) • 112-pin LQFP without external bus interface • 80-pin QFP without external bus interface 42 NOTE Appendix D Derivative Differences and Table 1-9. Pin-Out Summary MC9S12XE-Family Reference Manual Rev. 1.25 for more Table 1-7. Port for Freescale Semiconductor ...

Page 43

... N PC2 PC3 PB2 PC7 P PB0 PB3 PB4 PC4 R N.C. PB5 PB6 PB7 T N.C. N.C. PC5 PL3 Figure 1-4. - Pin Assignments, 208 MAPBGA Package Freescale Semiconductor PM1 PF5 PF3 PF1 PJ6 PS6 PF6 PF4 PF2 PF0 TEST PS4 PK7 PM2 PM4 PJ5 PS7 PS2 ...

Page 44

... PAD16/AN16 104 PAD15/AN15 103 PAD07/AN07 102 PAD14/AN14 101 PAD06/AN06 100 PAD13/AN13 99 PAD05/AN05 98 PAD12/AN12 97 PAD04/AN04 96 PAD11/AN11 95 PAD03/AN03 94 PAD10/AN10 93 PAD02/AN02 92 PAD09/AN09 91 PAD01/AN01 90 PAD08/AN08 89 PAD00/AN00 88 VSS2 87 VDD 86 PD7/DATA7 85 PD6/DATA6 84 PD5/DATA5 83 PD4/DATA4 82 VDDX3 81 VSSX3 80 PA7/ADDR15 79 PA6/ADDR14 78 PA5/ADDR13 77 PA4/ADDR12 76 PA3/ADDR11 75 PA2/ADDR10 74 PA1/ADDR9 73 PA0/ADDR8 Freescale Semiconductor ...

Page 45

... TXD2/KWJ1/PJ1 21 RXD2/KWJ0/PJ0 22 MODC/BKGD 23 PB0 24 PB1 25 PB2 26 PB3 27 PB4 28 Figure 1-6. MC9S12XE-Family Pin Assignments 112-pin LQFP Package Freescale Semiconductor MC9S12XE-Family 112LQFP Pins shown in BOLD are not available on the 80 QFP package MC9S12XE-Family Reference Manual Rev. 1.25 Chapter 1 Device Overview MC9S12XE-Family 84 VRH 83 VDDA1 82 PAD15/AN15 81 PAD07/AN07 80 PAD14/AN14 79 ...

Page 46

... MC9S12XE-Family 8 80QFP VDDF 9 VSS1 PB0 16 PB1 17 PB2 18 PB3 19 PB4 20 MC9S12XE-Family Reference Manual Rev. 1.25 60 VRH 59 VDDA1 58 PAD07/AN07 57 PAD06/AN06 56 PAD05/AN05 55 PAD04/AN04 54 PAD03/AN03 53 PAD02/AN02 52 PAD01/AN01 51 PAD00/AN00 50 VSS2 49 VDD 48 PA7 47 PA6 46 PA5 45 PA4 44 PA3 43 PA2 42 PA1 41 PA0 Freescale Semiconductor ...

Page 47

... MODC/BKGD Figure 1-8. MC9S12XEA256/MC9S12XEA128 80-pin QFP Package Pin Assignment SPECIAL BOND-OUT TO PROVIDE ACCESS TO EXTRA ADC CHANNELS IN 80QFP. WARNING: NOT PIN-COMPATIBLE WITH REST OF FAMILY. THE MC9S12XET256 AND MC9S12XEG128 USE THE STANDARD 80QFP BOND-OUT, COMPATIBLE WITH OTHER FAMILY MEMBERS. Freescale Semiconductor ...

Page 48

... Chapter 1 Device Overview MC9S12XE-Family 1.2.2 Pin Assignment Overview Table 1-7 provides a summary of which Ports are available for each package option. Routing of pin functions is summarized in Table 1-9 provides a pin out summary listing the availability of individual pins for each package option. 48 Table 1-8. MC9S12XE-Family Reference Manual Rev. 1.25 Freescale Semiconductor ...

Page 49

... I/O Power Pairs VDDX/VSSX 1. The 9S12XEA256 is a special bondout for access to extra ADC channels in 80QFP. Available in 80QFP / 256K memory size only. WARNING: NOT PIN-COMPATIBLE WITH REST OF FAMILY. The 9S12XET256 is the standard 256K/80QFP bondout, compatible with other family members. Freescale Semiconductor 208 144 LQFP MAPBGA ...

Page 50

... Chapter 1 Device Overview MC9S12XE-Family Table 1-8. Peripheral - Port Routing Options PF[0] PF[1] PF[2] PF[3] PF[5:4] PF[7:6] PH[1:0] PH[3:2] PH[5:4] PH[7:6] PJ[0] PJ[1] PJ[2] PJ[3] PJ[4] PJ[5] PJ[7:6] X PL[1:0] PL[3:2] PL[5:4] PL[7:6] PM[1:0] O PM[3: PM[5: PM[7:6] O PP[3:0] PP[7:4] PR[7: MC9S12XE-Family Reference Manual Rev. 1.25 ( Freescale Semiconductor ...

Page 51

... VDDX VSSX Freescale Semiconductor O O Table 1-9. Pin-Out Summary (Sheet (1) QFP 2nd Pin 80 Func. 1 PP3 KWP3 2 PP2 KWP2 3 PP1 KWP1 4 PP0 KWP0 PJ3 KWJ3 PJ2 KWJ2 PK6 ADDR22 ...

Page 52

... PB2 ADDR2 19 PB3 ADDR3 20 PB4 ADDR4 21 PB5 ADDR5 22 PB6 ADDR6 23 PB7 ADDR7 PC4 DATA12 MC9S12XE-Family Reference Manual Rev. 1.25 3rd 4th 5th Func. Func. Func. VREGAPI ACC1 ACC0 TXD2 RXD2 CS3 IVD0 UDS IVD1 IVD2 IVD3 IVD4 IVD5 IVD6 IVD7 Freescale Semiconductor ...

Page 53

... R9/ T10 59 47 R10/T11 N10 61 49 P10 R11 62 50 T12 Freescale Semiconductor Table 1-9. Pin-Out Summary (Sheet (1) QFP 2nd Pin 80 Func. PC5 DATA13 PC6 DATA14 PC7 DATA15 PL3 TXD5 PH7 KWH7 PL2 RXD5 PH6 KWH6 PL1 TXD4 ...

Page 54

... ADDR14 48 PA7 ADDR15 VSSX3 VDDX3 PD4 DATA4 PD5 DATA5 PD6 DATA6 PD7 DATA7 49 VDD 50 VSS2 MC9S12XE-Family Reference Manual Rev. 1.25 3rd 4th 5th Func. Func. Func. MOSI1 TXD6 MISO1 RXD6 LDS EROMCTL WE IVD8 IVD9 IVD10 IVD11 IVD12 IVD13 IVD14 IVD15 Freescale Semiconductor ...

Page 55

... D16 E15 101 79 C16 102 80 D15 C15 103 81 E14 104 82 B15 C14 105 D14 106 F13 107 83 Freescale Semiconductor Table 1-9. Pin-Out Summary (Sheet (1) QFP 2nd Pin 80 Func. 51 PAD00 AN00 PAD08 AN08 PAD24 AN24 52 PAD01 AN01 PAD09 AN09 PAD25 AN25 ...

Page 56

... PJ6 KWJ6 PJ5 KWJ5 PF0 CS0 PJ4 KWJ4 PF1 CS1 70 PM5 TXCAN2 MC9S12XE-Family Reference Manual Rev. 1.25 3rd 4th 5th Func. Func. Func. TXCAN4 TXD3 RXCAN4 RXD3 TXCAN4 SCL0 TXCAN0 RXCAN4 SDA0 RXCAN0 SCL1 CS2 SDA1 CS0 TXCAN0 TXCAN4 SCK0 Freescale Semiconductor ...

Page 57

... C5 140 108 A3 141 109 B3 142 110 C4 143 111 C3 144 112 1. Standard 80QFP only. NOTE that XEA256 80QFP is not compatible Freescale Semiconductor Table 1-9. Pin-Out Summary (Sheet (1) QFP 2nd Pin 80 Func. PF2 CS2 71 PM4 RXCAN2 PF3 CS3 72 PM3 TXCAN1 ...

Page 58

... Port E Input, maskable interrupt PUCR Up Port E input, non-maskable interrupt PERF/ Up Port F I/O, interrupt, TXD of PPSF SCI3 PERF/ Up Port F I/O, interrupt, RXD of PPSF SCI3 PERF/ Up Port F I/O, interrupt, SCL of PPSF IIC0 PERF/ Up Port F I/O, interrupt, SDA of PPSF IIC0 PERF/ Up Port F I/O, interrupt, chip PPSF select 3 Freescale Semiconductor ...

Page 59

... PJ5 KWJ5 SCL1 PJ4 KWJ4 SDA1 PJ3 KWJ3 — PJ2 KWJ2 CS1 PJ1 KWJ1 TXD2 PJ0 KWJ0 RXD2 PK7 EWAIT ROMCTL Freescale Semiconductor Pin Pin Power Name Name Supply Function 4 Function 5 — — V DDX — — V DDX — — V DDX TXD5 — ...

Page 60

... CAN4, MOSI of SPI0 CAN0 SPI0 CAN0, MISO of SPI0 PERP/ Disabled Port P I/O, interrupt, channel PPSP 7 of PWM/TIM , SCK of SPI2 PERP/ Disabled Port P I/O, interrupt, channel PPSP 6 of PWM/TIM SPI2 PERP/ Disabled Port P I/O, interrupt, channel PPSP 5 of PWM/TIM, MOSI of SPI2 Freescale Semiconductor ...

Page 61

... MISO0 — PS3 TXD1 — PS2 RXD1 — PS1 TXD0 — PS0 RXD0 — PT[7:6] IOC[7:6] — PT[5] IOC[5] VREGAPI PT[4:0] IOC[4:0] — Freescale Semiconductor Pin Pin Power Name Name Supply Function 4 Function 5 MISO2 TIMIOC4 V DDX SS1 TIMIOC3 V DDX SCK1 TIMIOC2 V DDX MOSI1 TIMIOC1 ...

Page 62

... PAD[15:0] are general-purpose input or output pins and analog inputs AN[15:0] of the analog-to-digital converter ATD0. 1.2.3.6 PAD[31:16] / AN[31:16] — Port AD Input Pins of ATD1 PAD[31:16] are general-purpose input or output pins and analog inputs AN[31:16] of the analog-to-digital converter ATD1. 62 NOTE Table 1-10 for affected pins. Particular attention is NOTE in all applications. SS MC9S12XE-Family Reference Manual Rev. 1.25 Freescale Semiconductor ...

Page 63

... Pierce oscillator is used or whether full swing Pierce oscillator/external clock circuitry is used (refer to Configuration). An internal pullup is enabled during reset. Freescale Semiconductor MC9S12XE-Family Reference Manual Rev. 1.25 Chapter 1 Device Overview MC9S12XE-Family ...

Page 64

... PE0 / XIRQ — Port E Input Pin 0 PE0 is a general-purpose input pin and the non-maskable interrupt request input that provides a means of applying asynchronous interrupt requests. This will wake up the MCU from stop or wait mode. The XIRQ 64 MC9S12XE-Family Reference Manual Rev. 1.25 Freescale Semiconductor ...

Page 65

... PH5 is a general-purpose input or output pin. It can be configured as a keypad wakeup input. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the serial peripheral interface 2 (SPI2). It can be configured as the transmit pin TXD of serial communication interface 4 (SCI4). Freescale Semiconductor MC9S12XE-Family Reference Manual Rev. 1.25 Chapter 1 Device Overview MC9S12XE-Family 65 ...

Page 66

... PJ6 is a general-purpose input or output pin. It can be configured as a keypad wakeup input. It can be configured as the receive pin RXCAN for the scalable controller area network controller (CAN0 or CAN4 the serial data pin SDA of the IIC0 module. 66 MC9S12XE-Family Reference Manual Rev. 1.25 Freescale Semiconductor ...

Page 67

... ACC[2:0] signals are used to indicate the access source of the bus cycle. These pins also provide the expanded addresses ADDR[22:20] for the external bus. In Emulation modes ACC[2:0] is available and is time multiplexed with the high addresses Freescale Semiconductor MC9S12XE-Family Reference Manual Rev. 1.25 Chapter 1 Device Overview MC9S12XE-Family ...

Page 68

... PL1 is a general-purpose input or output pin. It can be configured as the transmit pin TXD of serial communication interface 4 (SCI4). 1.2.3.51 PL0 / RXD4 — Port L I/O Pin 0 PL0 is a general-purpose input or output pin. It can be configured as the receive pin RXD of serial communication interface 4 (SCI4). 68 MC9S12XE-Family Reference Manual Rev. 1.25 Freescale Semiconductor ...

Page 69

... PM0 / RXCAN0 — Port M I/O Pin 0 PM0 is a general-purpose input or output pin. It can be configured as the receive pin RXCAN of the scalable controller area network controller 0 (CAN0). Freescale Semiconductor MC9S12XE-Family Reference Manual Rev. 1.25 Chapter 1 Device Overview MC9S12XE-Family 69 ...

Page 70

... PP1 is a general-purpose input or output pin. It can be configured as a keypad wakeup input. It can be configured as pulse width modulator (PWM) channel 1 output, TIM channel 1, or master output (during master mode) or slave input pin (during slave mode) MOSI of the serial peripheral interface 1 (SPI1). 70 MC9S12XE-Family Reference Manual Rev. 1.25 Freescale Semiconductor ...

Page 71

... PS2 is a general-purpose input or output pin. It can be configured as the receive pin RXD of serial communication interface 1 (SCI1). 1.2.3.75 PS1 / TXD0 — Port S I/O Pin 1 PS1 is a general-purpose input or output pin. It can be configured as the transmit pin TXD of serial communication interface 0 (SCI0). Freescale Semiconductor MC9S12XE-Family Reference Manual Rev. 1.25 Chapter 1 Device Overview MC9S12XE-Family 71 ...

Page 72

... VDD. The voltage supply of nominally 1.8V is derived from the internal voltage regulator. The return current path is through the VSS1,VSS2 and VSS3 pins. No static external loading of these pins is permitted. 72 NOTE MC9S12XE-Family Reference Manual Rev. 1.25 pins are connected together internally. SSX is tied to ground DDR Freescale Semiconductor ...

Page 73

... VDDA2 VDDA1 VSSA2 , VSSA1 VRL VRH VDD VSS1, VSS2, VSS3 VDDF Freescale Semiconductor VSSA1 — Power Supply Pins for ATD and , pins are connected together. Internally the V Nominal Description Voltage 5.0 V External power supply to internal voltage regulator 5.0 V External power and ground, supply to pin ...

Page 74

... Table 1-11. Power and Ground Connection Summary (continued) Mnemonic VDDPLL VSSPLL 74 Nominal Description Voltage 1.8 V Provides operating voltage and ground for the phased-locked loop. This allows the 0 V supply voltage to the PLL to be bypassed independently. Internal power and ground generated by internal regulator. MC9S12XE-Family Reference Manual Rev. 1.25 Freescale Semiconductor ...

Page 75

... The clock generated by the PLL or oscillator provides the main system clock frequencies core clock and bus clock. As shown in Figure the memories, and the peripherals. Freescale Semiconductor shows the clock connections from the CRG to all modules. CAN0 . . CAN4 Oscillator Clock Core Clock ...

Page 76

... MMCCTL1 register defines if the on chip flash memory is the memory map, or not. (See a detailed explanation of the ROMON and EROMON bits refer to the MMC description. 76 1.4.1 Chip Configuration 1.4.2 Power Modes. MC9S12XE-Family Reference Manual Rev. 1.25 Summary. 1.4.3 Freeze Mode. 1.4.4 System States. Table Freescale Semiconductor 1-12.) For ...

Page 77

... Developers use this mode for emulation systems in which the users target application is normal expanded mode. Code is executed from external memory or from internal memory depending on the state of ROMON and EROMON bit. In this mode the internal operation is visible on external bus interface. Freescale Semiconductor Table 1-12. Chip Modes and Data Sources MODB ...

Page 78

... API and ATD modules may be enabled. Other peripherals are turned off. This mode consumes more current than system stop mode but, as the oscillator continues to run, the full speed wake up time from this mode is significantly shorter. 78 MC9S12XE-Family Reference Manual Rev. 1.25 Freescale Semiconductor ...

Page 79

... This state is intended for configuring the MPU for different tasks that are then executed in User state, returning to Supervisor state on completion of each task. This is the default ’state’ following reset and can be re-entered from User state by an exception (interrupt). If the SVSEN bit in the MPUSEL register of the Freescale Semiconductor MC9S12XE-Family Reference Manual Rev. 1.25 Chapter 1 Device Overview MC9S12XE-Family ...

Page 80

... Low Voltage Reset (LVR) External pin RESET Illegal Address Reset Clock monitor reset COP watchdog reset MC9S12XE-Family Reference Manual Rev. 1.25 CCR Local Enable Mask None None None None None None None None None PLLCTL (CME, SCME) None COP rate select Freescale Semiconductor ...

Page 81

... Vector base + $CA $65 Vector base + $C8 $64 Vector base + $C6 $63 Vector base + $C4 $62 Vector base + $C2 $61 Vector base + $C0 $60 Freescale Semiconductor CCR Interrupt Source Mask Unimplemented instruction trap None SWI None XIRQ IRQ Real time interrupt Enhanced capture timer overflow Pulse accumulator A overflow ...

Page 82

... OVRIE) CAN3RIER (RXFIE) No CAN3TIER No (TXEIE[2:0]) CAN4RIER (WUPIE) Yes CAN4RIER (CSCIE, No OVRIE) CAN4RIER (RXFIE) No CAN4TIER No (TXEIE[2:0]) PIEP (PIEP7-PIEP0) Yes PWMSDN (PWMIE) No Freescale Semiconductor WAIT Yes Yes No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes ...

Page 83

... Vector base + $5A $2D Vector base + $58 $2C Vector base + $56 $2B Vector base + $54 $2A Vector base + $52 $29 Vector base + $50 $28 Freescale Semiconductor CCR Interrupt Source Mask SCI2 SCI3 SCI4 SCI5 IIC1 Bus Low-voltage interrupt (LVI) High Temperature Interrupt Periodic interrupt timer channel 0 Periodic interrupt timer channel 1 ...

Page 84

... PACTL (PAI bit ATD0CTL2 (ACMPIE) Yes I bit ATD1CTL2 (ACMPIE) Yes None None No None None No — None — — None — in the device electrical RST Freescale Semiconductor WAIT Wake up Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No — — ...

Page 85

... Flash configuration field byte at global address $7FFF0E during the reset sequence. If the MCU is secured the COP timeout rate is always set to the longest period (CR[2:0] = 111) after COP reset. FOPT Register FOPT Register Freescale Semiconductor Table 1-15 and Table 1-16 Table 1-15. Initial COP Rate Configuration ...

Page 86

... Periodic interrupt timer hardware trigger 0 Periodic interrupt timer hardware trigger 1 Table 1-18. ATD1 External Trigger Sources Connectivity Pulse width modulator channel 1 Pulse width modulator channel 3 Periodic interrupt timer hardware trigger 0 Periodic interrupt timer hardware trigger 1 MC9S12XE-Family Reference Manual Rev. 1.25 Table 1-17 Table 1- Freescale Semiconductor ...

Page 87

... BDM Clock Configuration The BDM alternate clock source is the oscillator clock. 1.12 S12XEPIM Configuration On smaller derivatives the S12XEPIM module is a subset of the S12XEP100. The registers of the unavailable ports are unimplemented. Freescale Semiconductor MC9S12XE-Family Reference Manual Rev. 1.25 Chapter 1 Device Overview MC9S12XE-Family and HTIA 87 ...

Page 88

... Figure 1-12. External Clock Connections (XCLKS = 0) 88 EXTAL C 1 MCU Crystal or Ceramic Resonator XTAL Ceramic Resonator R S =1MΩ specified by crystal vendor B S CMOS-Compatible EXTAL External Oscillator MCU XTAL Not Connected MC9S12XE-Family Reference Manual Rev. 1.25 V SSPLL C 1 Crystal SSPLL Freescale Semiconductor ...

Page 89

... Port AD0 and AD1 associated with two 16-channel ATD modules • Port R associated with 1 standard timer (TIM) module • Port L associated with 4 SCI modules Freescale Semiconductor Table 2-1. Revision History Sections Affected • Corrected reduced drive strength to 1/5 • Separated PE1,0 bit descriptions from other PE GPIO 2.3.19/120 • ...

Page 90

... Optional features supported on dedicated pins: • Open drain for wired-or connections • Interrupt inputs with glitch filtering • Reduced input threshold to support low voltage applications 2.2 External Signal Description This section lists and describes the signals that do connect off-chip. 90 NOTE MC9S12XE-Family Reference Manual Rev. 1.25 Freescale Semiconductor ...

Page 91

... IVD0 UDS GPIO C PC[7:0] DATA[15:8] GPIO D PD[7:0] DATA[7:0] GPIO Freescale Semiconductor NOTE Table 2-2. Pin Functions and Priorities I/O Description I MODC input during RESET I/O S12X_BDM communication pin O High-order external bus address output (multiplexed with IVIS data) I/O General-purpose I/O O Low-order external bus address output (multiplexed with IVIS data) ...

Page 92

... Configurable for reduced input threshold I/O General-purpose I/O O Extended external bus address output (multiplexed with access master output) I/O General-purpose I/O O Extended external bus address output (multiplexed with instruction pipe status bits) I/O General-purpose I/O MC9S12XE-Family Reference Manual Rev. 1.25 Pin Function after Reset Mode 4 dependent Mode 3 dependent Freescale Semiconductor ...

Page 93

... GPIO PS2 RXD1 GPIO PS1 TXD0 GPIO PS0 RXD0 GPIO Freescale Semiconductor I/O Description I/O Enhanced Capture Timer Channels 7 input/output I/O General-purpose I/O I/O Enhanced Capture Timer Channel 5 input/output O VREG Autonomous Periodical Interrupt output I/O General-purpose I/O I/O Enhanced Capture Timer Channels input/output I/O General-purpose I/O I/O Serial Peripheral Interface 0 slave select output in master mode, input in slave mode or master mode ...

Page 94

... I/O Serial Peripheral Interface 0 slave select output in master mode, input for slave mode or master mode. I/O General-purpose I/O I MSCAN1 receive pin I MSCAN0 receive pin I/O Serial Peripheral Interface 0 master in/slave out pin I/O General-purpose I/O O MSCAN0 transmit pin I/O General-purpose I/O I MSCAN0 receive pin I/O General-purpose I/O MC9S12XE-Family Reference Manual Rev. 1.25 Pin Function after Reset GPIO Freescale Semiconductor ...

Page 95

... MOSI1 (TIMIOC1) GPIO/KWP1 PP0 PWM0 MISO1 (TIMIOC0) GPIO/KWP0 Freescale Semiconductor I/O Description I/O Pulse Width Modulator input/output channel 7 I/O Serial Peripheral Interface 2 serial clock pin I/O Timer Channel 7 input/output I/O General-purpose I/O with interrupt O Pulse Width Modulator output channel 6 I/O Serial Peripheral Interface 2 slave select output in master mode, input for slave mode or master mode ...

Page 96

... I/O General-purpose I/O with interrupt I/O Serial Peripheral Interface 1 master out/slave in pin O Serial Communication Interface 6 transmit pin I/O General-purpose I/O with interrupt I/O Serial Peripheral Interface 1 master in/slave out pin O Serial Communication Interface 6 transmit pin I/O General-purpose I/O with interrupt MC9S12XE-Family Reference Manual Rev. 1.25 Pin Function after Reset GPIO Freescale Semiconductor ...

Page 97

... GPIO/KWJ0 AD0 PAD[15:0] GPIO AN[15:0] AD1 PAD[31:16] GPIO AN[15:0] R PR[7:0] TIMIOC[7:0] GPIO Freescale Semiconductor I/O Description O MSCAN4 transmit pin O Inter Integrated Circuit 0 serial clock line O MSCAN0 transmit pin I/O General-purpose I/O with interrupt I MSCAN4 receive pin I/O Inter Integrated Circuit 0 serial data line I MSCAN0 receive pin I/O General-purpose I/O with interrupt ...

Page 98

... Serial Communication Interface 3 receive pin I/O General-purpose I/O O Inter Integrated Circuit 0 serial clock line I/O General-purpose I/O I/O Inter Integrated Circuit 0 serial data line I/O General-purpose I/O O Chip select 3 I/O General-purpose I/O O Chip select 2 I/O General-purpose I/O O Chip select 1 I/O General-purpose I/O O Chip select 0 I/O General-purpose I/O MC9S12XE-Family Reference Manual Rev. 1.25 Pin Function after Reset GPIO GPIO Freescale Semiconductor ...

Page 99

... DDRE6 DDRE W 0x000A R 0x000B W Non-PIM Address Range 0x000C R PUPKE BKPUE PUCR W 0x000D R 0 RDPK RDRIV W = Unimplemented or Reserved Freescale Semiconductor 5 4 PA5 PA4 PB5 PB4 DDRA5 DDRA4 DDRA3 DDRB5 DDRB4 DDRB3 PC5 PC4 PD5 PD4 DDRC5 DDRC4 DDRC3 DDRD5 DDRD4 DDRD3 PE5 ...

Page 100

... DDRT5 DDRT4 DDRT3 RDRT5 RDRT4 RDRT3 MC9S12XE-Family Reference Manual Rev. 1. EDIV2 EDIV1 PK3 PK2 PK1 DDRK2 DDRK1 PTT2 PTT1 PTIT2 PTIT1 DDRT2 DDRT1 RDRT2 RDRT1 Freescale Semiconductor Bit 0 EDIV0 PK0 DDRK0 PTT0 PTIT0 DDRT0 RDRT0 ...

Page 101

... Reserved W 0x0250 R PTM7 PTM6 PTM W 0x0251 R PTIM7 PTIM6 PTIM W 0x0252 R DDRM7 DDRM6 DDRM W = Unimplemented or Reserved Freescale Semiconductor 5 4 PERT5 PERT4 PERT3 PPST5 PPST4 PPST3 PTS5 PTS4 PTS3 PTIS5 PTIS4 PTIS3 DDRS5 DDRS4 DDRS3 RDRS5 RDRS4 RDRS3 PERS5 ...

Page 102

... PTP2 PTP1 PTIP2 PTIP1 DDRP2 DDRP1 RDRP2 RDRP1 PERP2 PERP1 PPSP2 PPSP1 PIEP2 PIEP1 PIFP2 PIFP1 PTH2 PTH1 PTIH2 PTIH1 DDRH2 DDRH1 Freescale Semiconductor Bit 0 RDRM0 PERM0 PPSM0 WOMM0 MODRR0 PTP0 PTIP0 DDRP0 RDRP0 PERP0 PPSP0 PIEP0 PIFP0 PTH0 PTIH0 DDRH0 ...

Page 103

... PIEJ7 PIEJ6 PIEJ W 0x026F R PIFJ7 PIFJ6 PIFJ W 0x0270 R PT0AD07 PT0AD06 PT0AD0 W 0x0271 R PT1AD07 PT1AD06 PT1AD0 W = Unimplemented or Reserved Freescale Semiconductor 5 4 RDRH5 RDRH4 RDRH3 PERH5 PERH4 PERH3 PPSH5 PPSH4 PPSH3 PIEH5 PIEH4 PIEH3 PIFH5 PIFH4 PIFH3 PTJ5 PTJ4 PTJ3 PTIJ5 PTIJ4 PTIJ3 ...

Page 104

... PT0AD14 PT0AD13 PT1AD15 PT1AD14 PT1AD13 PER0AD15 PER0AD14 PER0AD13 PER1AD15 PER1AD14 PER1AD13 Non-PIM Address Range MC9S12XE-Family Reference Manual Rev. 1. PER0AD02 PER0AD01 PER0AD00 PER1AD02 PER1AD01 PER1AD00 PT0AD12 PT0AD11 PT1AD12 PT1AD11 PER0AD12 PER0AD1‘ PER0AD10 PER1AD12 PER1AD11 PER1AD10 Freescale Semiconductor Bit 0 PT0AD10 PT1AD10 ...

Page 105

... R PERL7 PERL6 PERL W 0x0375 R PPSL7 PPSL6 PPSL W 0x0376 R WOML7 WOML6 WOML W 0x0377 R PTLRR7 PTLRR6 PTLRR W = Unimplemented or Reserved Freescale Semiconductor 5 4 PTR5 PTR4 PTR3 PTIR5 PTIR4 PTIR3 DDRR5 DDRR4 DDRR3 RDRR5 RDRR4 RDRR3 PERR5 PERR4 PERR3 PPSR5 PPSR4 PPSR3 0 0 PTRRR5 PTRRR4 ...

Page 106

... RDRF3 PERF5 PERF4 PERF3 PPSF5 PPSF4 PPSF3 0 0 PTFRR5 PTFRR4 PTFRR3 MC9S12XE-Family Reference Manual Rev. 1. PTF2 PTF1 PTIF2 PTIF1 DDRF2 DDRF1 RDRF2 RDRF1 PERF2 PERF1 PPSF2 PPSF1 PTFRR2 PTFRR1 Freescale Semiconductor Bit 0 PTF0 PTIF0 DDRF0 RDRF0 PERF0 PPSF0 0 PTFRR0 ...

Page 107

... Always “0” on Port AD0, and AD1. 2. Applicable only on Port P, H, and J. All register bits in this module are completely synchronous to internal clocks during a register read. Freescale Semiconductor Table 2-3. Pin Configuration Summary (1) ( Function x 0 ...

Page 108

... MC9S12XE-Family Reference Manual Rev. 1.25 Access: User read/write PA2 PA1 ADDR9 ADDR10 mux mux IVD10 IVD9 Access: User read/write PB2 PB1 ADDR1 ADDR2 mux mux IVD2 IVD1 Freescale Semiconductor (1) 0 PA0 ADDR8 mux IVD8 0 (1) 0 PB0 ADDR0 mux IVD0 or UDS 0 ...

Page 109

... Figure 2-4. Port B Data Direction Register (DDRB) 1. Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value. Write: Anytime. In emulation modes, write operations will also be directed to the external bus. Freescale Semiconductor Description 5 4 ...

Page 110

... Table 2-7. DDRB Register Field Descriptions Description 5 4 PC5 PC4 PC3 DATA13 DATA12 DATA11 0 0 Figure 2-5. Port C Data Register (PORTC) Description MC9S12XE-Family Reference Manual Rev. 1.25 Access: User read/write PC2 PC1 DATA10 DATA9 Freescale Semiconductor (1) 0 PC0 DATA8 0 ...

Page 111

... Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value. Write: Anytime. In emulation modes, write operations will also be directed to the external bus. Freescale Semiconductor 5 4 PD5 ...

Page 112

... When operating a pin as a general purpose I/O, the associated data direction bit determines whether input or output. 1 Associated pin is configured as output. 0 Associated pin is configured as high-impedance input. 112 Description 5 4 DDRD5 DDRD4 DDRD3 0 0 Description MC9S12XE-Family Reference Manual Rev. 1.25 Access: User read/write DDRD2 DDRD1 Freescale Semiconductor (1) 0 DDRD0 0 ...

Page 113

... Port E general purpose input data and interrupt—Data Register, IRQ input. PE This pin can be used as general purpose and IRQ input. 0 Port E general purpose input data and interrupt—Data Register, XIRQ input. PE This pin can be used as general purpose and XIRQ input. Freescale Semiconductor 5 4 PE5 PE4 PE3 MODA ...

Page 114

... Write:Anytime, except BKPUE which is writable in Special Test Mode only. 114 5 4 DDRE5 DDRE4 DDRE3 0 0 Description PUPEE PUPDE 0 1 MC9S12XE-Family Reference Manual Rev. 1.25 Access: User read/write DDRE2 Access: User read/write PUPCE PUPBE Freescale Semiconductor ( (1) 0 PUPAE 0 ...

Page 115

... This bit configures whether pull-up devices are activated, if the pins are used as inputs. This bit has no effect if the pins are used as outputs. Out of reset the pull-up devices are disabled. 1 Pull-up devices enabled. 0 Pull-up devices disabled. Freescale Semiconductor Description MC9S12XE-Family Reference Manual Rev. 1.25 Chapter 2 Port Integration Module (S12XEPIMV1) ...

Page 116

... If a pin is used as input this bit has no effect. 1 Reduced drive selected (approx. 1/5 of the full drive strength). 0 Full drive strength enabled. 116 RDPE RDPD 0 0 Description MC9S12XE-Family Reference Manual Rev. 1.25 Access: User read/write RDPC RDPB Freescale Semiconductor (1) 0 RDPA 0 ...

Page 117

... Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value. Write: Anytime. In emulation modes, write operations will also be directed to the external bus. 2. Reset values in emulation modes are identical to those of the target mode. Freescale Semiconductor Description 5 4 ...

Page 118

... PIM Reserved Register Address 0x001D (PRR Reset Unimplemented or Reserved 1. Read: Always reads 0x00 Write: Unimplemented 118 Description Figure 2-14. PIM Reserved Register MC9S12XE-Family Reference Manual Rev. 1.25 Access: User read Freescale Semiconductor ( ...

Page 119

... This register is reserved for factory testing of the PIM module and is not available in normal operation. Address 0x001F Reset Unimplemented or Reserved 1. Read: Always reads 0x00 Write: Unimplemented Writing to this register when in special modes can alter the pin functionality. Freescale Semiconductor Figure 2-15. IRQ Control Register (IRQCR) Description Figure 2-16 ...

Page 120

... Figure 2-17. Port K Data Register (PORTK) Description 5 4 DDRK5 DDRK4 DDRK3 0 0 MC9S12XE-Family Reference Manual Rev. 1.25 Access: User read/write PK2 PK1 ADDR18 ADDR17 mux mux IQSTAT2 IQSTAT1 Access: User read/write DDRK2 DDRK1 Freescale Semiconductor (1) 0 PK0 ADDR16 mux IQSTAT0 0 (1) 0 DDRK0 0 ...

Page 121

... Port T pins 4 through 0 are associated with ECT channels IOC4 through IOC0. When not used with the alternative function, these pins can be used as general purpose I/O. If the associated data direction bit of this pin is set read returns the value of the port register, otherwise the buffered pin input state is read. Freescale Semiconductor Description 5 4 ...

Page 122

... Table 2-21. PTIT Register Field Descriptions Description 5 4 DDRT5 DDRT4 DDRT3 0 0 Table 2-22. DDRT Register Field Descriptions Description MC9S12XE-Family Reference Manual Rev. 1.25 Access: User read PTIT2 PTIT1 Access: User read/write DDRT2 DDRT1 Freescale Semiconductor (1) 0 PTIT0 u (1) 0 DDRT0 0 ...

Page 123

... PERT These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect if the pin is used as an output. Out of reset no pull device is enabled. 1 Pull device enabled. 0 Pull device disabled. Freescale Semiconductor NOTE 5 4 RDRT5 RDRT4 ...

Page 124

... Figure 2-25. PIM Reserved Register Figure 2-26. PIM Reserved Register MC9S12XE-Family Reference Manual Rev. 1.25 Access: User read/write PPST2 PPST1 Access: User read Access: User read Freescale Semiconductor (1) 0 PPST0 ...

Page 125

... Port S bits 2 is associated with the RXD signal of the SCI1 module. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set read returns the value of the port register, otherwise the buffered pin input state is read. Freescale Semiconductor 5 4 PTS5 ...

Page 126

... Unaffected by reset Figure 2-28. Port S Input Register (PTIS) Table 2-27. PTIS Register Field Descriptions Description 5 4 DDRS5 DDRS4 DDRS3 0 0 MC9S12XE-Family Reference Manual Rev. 1.25 Access: User read PTIS2 PTIS1 Access: User read/write DDRS2 DDRS1 Freescale Semiconductor (1) 0 PTIS0 u (1) 0 DDRS0 0 ...

Page 127

... This register configures the drive strength of output pins 7 through 0 as either full or reduced independent of the function used on the pins pin is used as input this bit has no effect. 1 Reduced drive selected (approx. 1/5 of the full drive strength). 0 Full drive strength enabled. Freescale Semiconductor Description NOTE 5 ...

Page 128

... Table 2-30. PERS Register Field Descriptions Description 5 4 PPSS5 PPSS4 PPSS3 0 0 Table 2-31. PPSS Register Field Descriptions Description MC9S12XE-Family Reference Manual Rev. 1.25 Access: User read/write PERS2 PERS1 Access: User read/write PPSS2 PPSS1 Freescale Semiconductor (1) 0 PERS0 1 (1) 0 PPSS0 0 ...

Page 129

... Output buffers operate as open-drain outputs. 0 Output buffers operate as push-pull outputs. 2.3.36 PIM Reserved Register Address 0x024F Reset Unimplemented or Reserved 1. Read: Always reads 0x00 Write: Unimplemented Freescale Semiconductor 5 4 WOMS5 WOMS4 WOMS3 0 0 Description Unaffected by reset Figure 2-34. PIM Reserved Register MC9S12XE-Family Reference Manual Rev ...

Page 130

... Figure 2-35. Port M Data Register (PTM) Table 2-33. PTM Register Field Descriptions Description MC9S12XE-Family Reference Manual Rev. 1.25 Access: User read/write PTM2 PTM1 RXCAN1 TXCAN0 (RXCAN0) — — — — (MISO0) — — — — Freescale Semiconductor (1) 0 PTM0 RXCAN0 — — — — 0 ...

Page 131

... Port M Input Register (PTIM) Address 0x0251 PTIM7 PTIM6 W Reset Unimplemented or Reserved Freescale Semiconductor Description 5 4 PTIM5 PTIM4 PTIM3 Unaffected by reset Figure 2-36. Port M Input Register (PTIM) MC9S12XE-Family Reference Manual Rev. 1.25 Chapter 2 Port Integration Module (S12XEPIMV1) Access: User read ...

Page 132

... The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled. 1 Associated pin is configured as output. 0 Associated pin is configured as input. 132 Table 2-34. PTIM Register Field Descriptions Description 5 4 DDRM5 DDRM4 DDRM3 0 0 Description MC9S12XE-Family Reference Manual Rev. 1.25 Access: User read/write DDRM2 DDRM1 Freescale Semiconductor (1) 0 DDRM0 0 ...

Page 133

... Associated pin is configured as input. Due to internal synchronization circuits, it can take bus clock cycles until the correct value is read on PTM or PTIM registers, when changing the DDRM register. Freescale Semiconductor Description NOTE MC9S12XE-Family Reference Manual Rev. 1.25 Chapter 2 Port Integration Module (S12XEPIMV1) ...

Page 134

... Pull device enabled. 0 Pull device disabled. 134 5 4 RDRM5 RDRM4 RDRM3 0 0 Description 5 4 PERM5 PERM4 PERM3 0 0 Description MC9S12XE-Family Reference Manual Rev. 1.25 Access: User read/write RDRM2 RDRM1 Access: User read/write PERM2 PERM1 Freescale Semiconductor (1) 0 RDRM0 0 (1) 0 PERM0 0 ...

Page 135

... A logic level of “1” is not driven.This allows a multipoint connection of several serial modules. These bits have no influence on pins used as inputs. 1 Output buffers operate as open-drain outputs. 0 Output buffers operate as push-pull outputs. Freescale Semiconductor 5 4 PPSM5 PPSM4 ...

Page 136

... Access: User read/write MODRR2 MODRR1 Related Pins TXCAN PM1 PM3 PM5 PJ7 PJ7 PM5 PM7 Reserved MOSI SCK SS PS5 PS6 PS7 PM4 PM5 PM3 PP1 PP2 PP3 PH1 PH2 PH3 PP5 PP7 PP6 PH5 PH6 PH7 Freescale Semiconductor (1) 0 MODRR0 0 ...

Page 137

... When not used with the alternative functions, these pins can be used as general purpose I/O. If the associated data direction bits of these pins are set read returns the value of the port register, otherwise the buffered pin input state is read. Freescale Semiconductor 5 4 PTP5 ...

Page 138

... Reset Unimplemented or Reserved 1. Read: Anytime. Write:Never, writes to this register have no effect. 138 Description 5 4 PTIP5 PTIP4 PTIP3 Unaffected by reset Figure 2-44. Port P Input Register (PTIP) MC9S12XE-Family Reference Manual Rev. 1.25 Access: User read PTIP2 PTIP1 Freescale Semiconductor (1) 0 PTIP0 u ...

Page 139

... Associated pin is configured as output. 0 Associated pin is configured as input. Due to internal synchronization circuits, it can take bus clock cycles until the correct value is read on PTP or PTIP registers, when changing the DDRP register. Freescale Semiconductor Table 2-42. PTIP Register Field Descriptions Description 5 4 ...

Page 140

... RDRP5 RDRP4 RDRP3 0 0 Description 5 4 PPSP5 PPSP4 PPSP3 0 0 Table 2-45. PERP Register Field Descriptions Description MC9S12XE-Family Reference Manual Rev. 1.25 Access: User read/write RDRP2 RDRP1 Access: User read/write PPSP2 PPSP1 Freescale Semiconductor (1) 0 RDRP0 0 (1) 0 PPSP0 0 ...

Page 141

... Write: Anytime. Field 7-0 Port P interrupt enable— PIEP This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port P. 1 Interrupt is enabled. 0 Interrupt is disabled (interrupt flag masked). Freescale Semiconductor 5 4 PPSP5 PPSP4 PPSP3 0 0 Table 2-46. PPSP Register Field Descriptions ...

Page 142

... MISO2 SS1 TXD4 RXD4 TXD7 0 0 Figure 2-51. Port H Data Register (PTH) MC9S12XE-Family Reference Manual Rev. 1.25 Access: User read/write PIFP2 PIFP1 Access: User read/write PTH2 PTH1 SCK1 MOSI1 RXD7 TXD6 Freescale Semiconductor (1) 0 PIFP0 0 (1) 0 PTH0 MISO1 RXD6 0 ...

Page 143

... When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set read returns the value of the port register, otherwise the buffered pin input state is read. Freescale Semiconductor Table 2-49. PTH Register Field Descriptions Description MC9S12XE-Family Reference Manual Rev ...

Page 144

... Unaffected by reset Figure 2-52. Port H Input Register (PTIH) Table 2-50. PTIH Register Field Descriptions Description 5 4 DDRH5 DDRH4 DDRH3 0 0 MC9S12XE-Family Reference Manual Rev. 1.25 Access: User read PTIH2 PTIH1 Access: User read/write DDRH2 DDRH1 Freescale Semiconductor (1) 0 PTIH0 u (1) 0 DDRH0 0 ...

Page 145

... In those cases the data direction bits will not change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled. 1 Associated pin is configured as output. 0 Associated pin is configured as input. Freescale Semiconductor Description MC9S12XE-Family Reference Manual Rev. 1.25 Chapter 2 Port Integration Module (S12XEPIMV1) ...

Page 146

... If a pin is used as input this bit has no effect. 1 Reduced drive selected (approx. 1/5 of the full drive strength). 0 Full drive strength enabled. 146 Description NOTE 5 4 RDRH5 RDRH4 RDRH3 0 0 Description MC9S12XE-Family Reference Manual Rev. 1.25 Access: User read/write RDRH2 RDRH1 Freescale Semiconductor (1) 0 RDRH0 0 ...

Page 147

... Port H pin, if enabled by the associated bit in register PERH and if the port is used as input falling edge on the associated Port H pin sets the associated flag bit in the PIFH register.A pull-up device is connected to the associated Port H pin, if enabled by the associated bit in register PERH and if the port is used as input. Freescale Semiconductor 5 4 PERH5 PERH4 ...

Page 148

... Table 2-55. PPSP Register Field Descriptions Description 5 4 PIFH5 PIFH4 PIFH3 0 0 Table 2-56. PPSP Register Field Descriptions Description MC9S12XE-Family Reference Manual Rev. 1.25 Access: User read/write PIEH2 PIEH1 Access: User read/write PIFH2 PIFH1 Freescale Semiconductor (1) 0 PIEH0 0 (1) 0 PIFH0 0 ...

Page 149

... This pin is associated with the chip select output signal CS2. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set read returns the value of the port register, otherwise the buffered pin input state is read. Freescale Semiconductor 5 4 PTJ5 ...

Page 150

... Unaffected by reset Figure 2-60. Port J Input Register (PTIJ) Table 2-58. PTIJ Register Field Descriptions Description 5 4 DDRJ5 DDRJ4 DDRJ3 0 0 MC9S12XE-Family Reference Manual Rev. 1.25 Access: User read PTIJ2 PTIJ1 Access: User read/write DDRJ2 DDRJ1 Freescale Semiconductor (1) 0 PTIJ0 u (1) 0 DDRJ0 0 ...

Page 151

... The enabled CS1 signal forces the I/O state output. In those cases the data direction bits will not change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled. 1 Associated pin is configured as output. 0 Associated pin is configured as input. Freescale Semiconductor Table 2-59. DDRJ Register Field Descriptions Description MC9S12XE-Family Reference Manual Rev. 1.25 ...

Page 152

... Reduced drive selected (approx. 1/5 of the full drive strength). 0 Full drive strength enabled. 152 Description NOTE 5 4 RDRJ5 RDRJ4 RDRJ3 0 0 Table 2-60. RDRJ Register Field Descriptions Description MC9S12XE-Family Reference Manual Rev. 1.25 Access: User read/write RDRJ2 RDRJ1 Freescale Semiconductor (1) 0 RDRJ0 0 ...

Page 153

... Port J pin, if enabled by the associated bit in register PERJ and if the port is used as input falling edge on the associated Port J pin sets the associated flag bit in the PIFJ register.A pull-up device is connected to the associated Port J pin, if enabled by the associated bit in register PERJ and if the port is used as input. Freescale Semiconductor 5 4 PERJ5 PERJ4 ...

Page 154

... Table 2-63. PPSP Register Field Descriptions Description 5 4 PIFJ5 PIFJ4 PIFJ3 0 0 Table 2-64. PPSP Register Field Descriptions Description MC9S12XE-Family Reference Manual Rev. 1.25 Access: User read/write PIEJ2 PIEJ1 Access: User read/write PIFJ2 PIFJ1 Freescale Semiconductor (1) 0 PIEJ0 0 (1) 0 PIFJ0 0 ...

Page 155

... When not used with the alternative function, these pins can be used as general purpose I/O. If the associated data direction bits of these pins are set read returns the value of the port register, otherwise the buffered pin input state is read. Freescale Semiconductor 5 4 PT0AD05 ...

Page 156

... Read: Anytime. Write: Anytime. 156 5 4 DDR0AD05 DDR0AD04 DDR0AD03 0 0 Description NOTE NOTE 5 4 DDR1AD05 DDR1AD04 DDR1AD03 0 0 MC9S12XE-Family Reference Manual Rev. 1.25 Access: User read/write DDR0AD02 DDR0AD01 Access: User read/write DDR1AD02 DDR1AD01 Freescale Semiconductor (1) 0 DDR0AD00 0 (1) 0 DDR1AD00 0 ...

Page 157

... This register configures the drive strength of Port AD0 output pins 15 through 8 as either full or reduced independent of the function used on the pins pin is used as input this bit has no effect. 1 Reduced drive selected (approx. 1/5 of the full drive strength). 0 Full drive strength enabled. Freescale Semiconductor Description NOTE NOTE ...

Page 158

... Pull device enabled. 0 Pull device disabled. 158 5 4 RDR1AD05 RDR1AD04 RDR1AD03 0 0 Description 5 4 PER0AD05 PER0AD04 PER0AD03 0 0 Description MC9S12XE-Family Reference Manual Rev. 1.25 Access: User read/write RDR1AD02 RDR1AD01 Access: User read/write PER0AD02 PER0AD01 Freescale Semiconductor (1) 0 RDR1AD00 0 (1) 0 PER0AD00 0 ...

Page 159

... When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bits of these pins are set read returns the value of the port register, otherwise the buffered pin input state is read. Freescale Semiconductor 5 4 PER1AD05 ...

Page 160

... PT1AD15 PT1AD14 PT1AD13 AN5 AN4 AN3 0 0 Description 5 4 DDR0AD15 DDR0AD14 DDR0AD13 0 0 Description MC9S12XE-Family Reference Manual Rev. 1.25 Access: User read/write PT1AD12 PT1AD11 AN2 AN1 Access: User read/write DDR0AD12 DDR0AD11 Freescale Semiconductor (1) 0 PT1AD10 AN0 0 (1) 0 DDR0AD10 0 ...

Page 161

... Due to internal synchronization circuits, it can take bus clock cycles until the correct value is read on PT0AD1 registers, when changing the DDR1AD1 register. To use the digital input function on Port AD1 the ATD Digital Input Enable Register (ATD1DIEN1) has to be set to logic level “1”. Freescale Semiconductor NOTE NOTE 5 4 ...

Page 162

... Full drive strength enabled. 162 5 4 RDR0AD15 RDR0AD14 RDR0AD13 0 0 Description 5 4 RDR1AD15 RDR1AD14 RDR1AD13 0 0 Description MC9S12XE-Family Reference Manual Rev. 1.25 Access: User read/write RDR0AD12 RDR0AD11 Access: User read/write RDR1AD12 RDR1AD11 Freescale Semiconductor (1) 0 RDR0AD10 0 (1) 0 RDR1AD10 0 ...

Page 163

... PER1AD1 These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect if the pin is used as an output. Out of reset no pull device is enabled. 1 Pull device enabled. 0 Pull device disabled. Freescale Semiconductor 5 4 PER0AD15 PER0AD14 PER0AD13 ...

Page 164

... Unaffected by reset Figure 2-84. Port R Input Register (PTIR) Table 2-82. PTIR Register Field Descriptions Description MC9S12XE-Family Reference Manual Rev. 1.25 Access: User read/write PTR2 PTR1 TIMIOC2 TIMIOC1 Access: User read PTIR2 PTIR1 Freescale Semiconductor (1) 0 PTR0 TIMIOC0 0 (1) 0 PTIR0 u ...

Page 165

... PTR or PTIR registers, when changing the DDRR register. 2.3.88 Port R Reduced Drive Register (RDRR) Address 0x036B RDRR7 RDRR6 W Reset 0 0 Figure 2-86. Port R Reduced Drive Register (RDRR) 1. Read: Anytime. Write: Anytime. Freescale Semiconductor 5 4 DDRR5 DDRR4 DDRR3 0 0 Description NOTE 5 4 RDRR5 RDRR4 RDRR3 0 0 MC9S12XE-Family Reference Manual Rev ...

Page 166

... Description 5 4 PERR5 PERR4 PERR3 0 0 Table 2-85. PERR Register Field Descriptions Description 5 4 PPSR5 PPSR4 PPSR3 0 0 MC9S12XE-Family Reference Manual Rev. 1.25 Access: User read/write PERR2 PERR1 Access: User read/write PPSR2 PPSR1 Freescale Semiconductor (1) 0 PERR0 0 (1) 0 PPSR0 0 ...

Page 167

... This register configures the re-routing of the associated TIM channel. 1 TIMIOC7 is available on PP7 0 TIMIOC7 is available on PR7 6 Port R routing— PTRRR This register configures the re-routing of the associated TIM channel. 1 TIMIOC6 is available on PP6 0 TIMIOC6 is available on PR6 Freescale Semiconductor Table 2-86. PPSR Register Field Descriptions Description Figure 2-89 ...

Page 168

... Function Reset Read: Anytime. Write: Anytime. 168 Description 5 4 PTL5 PTL4 PTL3 (TXD6) (RXD6) (TXD5 Figure 2-91. Port L Data Register (PTL) MC9S12XE-Family Reference Manual Rev. 1.25 Access: User read/write PTL2 PTL1 (RXD5) (TXD4 Freescale Semiconductor (1) 0 PTL0 (RXD4) 0 ...

Page 169

... When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set read returns the value of the port register, otherwise the buffered pin input state is read. Freescale Semiconductor Table 2-88. PTL Register Field Descriptions Description MC9S12XE-Family Reference Manual Rev ...

Page 170

... Table 2-89. PTIL Register Field Descriptions Description 5 4 DDRL5 DDRL4 DDRL3 0 0 Table 2-90. DDRL Register Field Descriptions Description MC9S12XE-Family Reference Manual Rev. 1.25 Access: User read PTIL2 PTIL1 Access: User read/write DDRL2 DDRL1 Freescale Semiconductor (1) 0 PTIL0 u (1) 0 DDRL0 0 ...

Page 171

... These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect if the pin is used as an output. Out of reset all pull devices are enabled. 1 Pull device enabled. 0 Pull device disabled. Freescale Semiconductor NOTE 5 4 RDRL5 ...

Page 172

... PPSL5 PPSL4 PPSL3 0 0 Table 2-93. PPSL Register Field Descriptions Description 5 4 WOML5 WOML4 WOML3 0 0 Description MC9S12XE-Family Reference Manual Rev. 1.25 Access: User read/write PPSL2 PPSL1 Access: User read/write WOML2 WOML1 Freescale Semiconductor (1) 0 PPSL0 0 (1) 0 WOML0 0 ...

Page 173

... Port F Data Register (PTF) Address 0x0378 PTF7 PTFT6 W Altern. (TXD3) (RXD3) Function Reset Read: Anytime. Write: Anytime. Freescale Semiconductor 5 4 PTLRR5 PTLRR4 0 0 Figure 2-98. Port L Routing Register (PTLRR) Table 2-95. Port L Routing Summary PTLRR Related Pins TXD SCI7 ...

Page 174

... When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set read returns the value of the port register, otherwise the buffered pin input state is read. 174 Table 2-96. PTF Register Field Descriptions Description MC9S12XE-Family Reference Manual Rev. 1.25 Freescale Semiconductor ...

Page 175

... SCI transmit channel is enabled forced input if the SCI receive channel is enabled. The data direction bits revert to controlling the I/O direction of a pin when the associated channel is disabled. 1 Associated pin is configured as output. 0 Associated pin is configured as input. Freescale Semiconductor 5 4 PTIF5 ...

Page 176

... RDRF5 RDRF4 RDRF3 0 0 Table 2-99. RDRF Register Field Descriptions Description 5 4 PERF5 PERF4 PERF3 1 1 Description MC9S12XE-Family Reference Manual Rev. 1.25 Access: User read/write RDRF2 RDRF1 Access: User read/write PERF2 PERF1 Freescale Semiconductor (1) 0 RDRF0 0 (1) 0 PERF0 1 ...

Page 177

... Write: Unimplemented 2.3.108 Port F Routing Register (PTFRR) Address 0x037F Reset Unimplemented or Reserved Figure 2-106. Port F Routing Register (PTFRR) 1. Read: Anytime. Write: Anytime. Freescale Semiconductor 5 4 PPSF5 PPSF4 PPSF3 0 0 Description Figure 2-105. PIM Reserved Register ...

Page 178

... Example 2-1. Selecting a pull-up device MC9S12XE-Family Reference Manual Rev. 1.25 Related Pins TXD RXD PM7 PM6 PF7 PF6 SCL SDA PJ7 PJ6 PF5 PF4 CS PJ0 PF3 PJ5 PF2 PJ2 PF1 PJ4 PF0 Freescale Semiconductor ...

Page 179

... This is a read-only register and always returns the buffered state of the pin 2.4.2.3 Data direction register (DDRx) This register defines whether the pin is used as an input or an output peripheral module controls the pin the contents of the data direction register is ignored Freescale Semiconductor Table 2-103. Register availability per port Reduced Pull Polarity ...

Page 180

... Interrupt enable register (PIEx) If the pin is used as an interrupt input this register serves as a mask to the interrupt flag to enable/disable the interrupt. 180 PTI DDR 0 1 data out output enable module enable MC9S12XE-Family Reference Manual Rev. 1.25 PIN Freescale Semiconductor ...

Page 181

... Port E pins PE[7:2] can be used for either general-purpose I/O or with the alternative functions. Port E pin PE[7] can be used for either general-purpose I the free-running clock ECLKX2 output running at the Core Clock rate. The clock output is always enabled in emulation modes. Freescale Semiconductor NOTE MC9S12XE-Family Reference Manual Rev. 1.25 ...

Page 182

... This port is associated with SCI0, SCI1 and SPI0. Port S pins PS[7:4] can be used either for general-purpose I/O, or with the SPI0 subsystem. Port S pins PS[3:2] can be used either for general-purpose I/O, or with the SCI1 subsystem. Port S pins PS[1:0] can be used either for general-purpose I/O, or with the SCI0 subsystem. 182 MC9S12XE-Family Reference Manual Rev. 1.25 Freescale Semiconductor ...

Page 183

... Port J pins PJ[7:6] can be used for either general purpose I/O, or with the CAN4, IIC0 or CAN0 subsystems. Port J pins PJ[5:4] can be used for either general purpose I/O, or with the IIC1 subsystem or as chip select outputs. Freescale Semiconductor MC9S12XE-Family Reference Manual Rev. 1.25 Chapter 2 Port Integration Module (S12XEPIMV1) 183 ...

Page 184

... This port is associated with SCI3, IIC0 and chip selects. Port L pins PL[7:6] can be used for either general purpose I/O, or with SCI3 subsystem. Port L pins PL[5:4] can be used for either general purpose I/O, or with IIC0 subsystem. Port L pins PL[3:0] can be used for either general purpose I/O, or with chip selects. 184 MC9S12XE-Family Reference Manual Rev. 1.25 Freescale Semiconductor ...

Page 185

... Figure 2-108. Interrupt Glitch Filter on Port P, H and J (PPS=0) Pulse Ignored Uncertain Valid 1. These values include the spread of the oscillator frequency over temper- ature, voltage and process. Freescale Semiconductor (Figure 2-109) shorter than a specified time from generating an uncertain t pign t pval Table 2-104 ...

Page 186

... It is not recommended to write PORTx/PTx and DDRx in a word access. When changing the register pins from inputs to outputs, the data may have extra transitions during the write access. Initialize the port data register before enabling the outputs. 186 t pulse Figure 2-109. Pulse Illustration MC9S12XE-Family Reference Manual Rev. 1.25 Freescale Semiconductor ...

Page 187

... The MMC module controls the multi-master priority accesses, the selection of internal resources and external space. Internal buses, including internal memories and peripherals, are controlled in this module. The local address space for each master is translated to a global memory space. Freescale Semiconductor Table 3-1. Revision History Sections Affected - Reorganization of MEMCTL0 register bits ...

Page 188

... Non-volatile Memory; Flash EEPROM or ROM 3.1.2 Features The main features of this block are: • Paging capability to support a global 8 Mbytes memory address space • Bus arbitration between the masters CPU, BDM and XGATE 188 Table 3-2. Acronyms and Abbreviations MC9S12XE-Family Reference Manual Rev. 1.25 Freescale Semiconductor ...

Page 189

... Functional Modes • Single chip modes In normal and special single chip mode the internal memory is used. External bus is not active. 1. Resources are also called targets. Freescale Semiconductor 1 (internal, external, and peripherals) (see MC9S12XE-Family Reference Manual Rev. 1.25 Chapter 3 Memory Mapping Control (S12XMMCV4) ...

Page 190

... Doted blocks and lines are optional. Please refer to the Device User Guide for their availlibilities. 190 CPU Address Decoder & Priority Target Bus Controller EBI RAM Figure 3-1. MMC Block Diagram MC9S12XE-Family Reference Manual Rev. 1.25 XGATE FLEXRAY Peripherals Freescale Semiconductor DBG ...

Page 191

... I Table 3-4. External Output Signals Associated with the MMC Signal I/O CS0 O CS1 O CS2 O CS3 O Freescale Semiconductor Description Mode input Mode input Mode input EROM control input ROM control input Description NS Chip select line 0 Chip select line 1 Chip select line 2 Chip select line 3 MC9S12XE-Family Reference Manual Rev ...

Page 192

... Figure 3-2. MMC Register Summary MC9S12XE-Family Reference Manual Rev. 1.25 Figure 3-2. Detailed descriptions Bit 0 CS1E1 CS1E0 CS0E1 CS0E0 GP3 GP2 GP1 GP0 DP11 DP10 DP9 DP8 ROMON PIX3 PIX2 PIX1 PIX0 RP3 RP2 RP1 RP0 EP3 EP2 EP1 EP0 Freescale Semiconductor ...

Page 193

... Availability of chip selects. (See • Control of different external stretch mechanism. For more detail refer to the S12X_EBI BlockGuide. XGATE write access to this register during an CPU access which makes use of this register could lead to unexpected results. Freescale Semiconductor 5 4 CS2E1 CS2E0 CS1E1 0 ...

Page 194

... Table 3-16) the CS2 is asserted in the space occupied by this on- Section 3.3.2.5, “MMC Control Register MC9S12XE-Family Reference Manual Rev. 1.25 Table 3-7 Table 3-7 Table 3-7 Table 3-7 Top Address (1) 0x0F_FFFF minus RAMSIZE 0x1F_FFFF 0x3F_FFFF (4) 0x7F_FFFF minus FLASHSIZE (MMCCTL1)) Freescale Semiconductor and and and and ...

Page 195

... In emulation modes reading this address returns data from the external bus which has to be driven by the emulator therefore responsibility of the emulator hardware to provide the expected value (i.e. a value corresponding to normal single chip mode while the device is in emulation single-chip mode or a value corresponding to normal expanded mode while the device is in emulation expanded mode). Freescale Semiconductor ...

Page 196

... Special Test (ST) 010 101 101 Special Single-Chip (SS) 000 000 RESET 110 111 MC9S12XE-Family Reference Manual Rev. 1.25 Normal 101 Expanded RESET (NX) 101 Emulation 011 Expanded RESET (EX) 011 Illegal (MODC, MODB, MODA) pin values. Do not use. (Reserved for future use). Freescale Semiconductor ...

Page 197

... Global Page Index Bits 6–0 — These page index bits are used to select which of the 128 64-kilobyte pages is GP[6: accessed. Example 3-1. This example demonstrates usage of the GPAGE register LDX #0x5000 MOVB #0x14, GPAGE GLDAA X Freescale Semiconductor 5 4 GP5 GP4 GP3 CAUTION ...

Page 198

... Y index register from 0x8000 (direct access). ;< operator forces direct access on some assemblers but in MC9S12XE-Family Reference Manual Rev. 1. DP10 DP9 0 0 Figure 3-9). Bit0 Bit7 Freescale Semiconductor 0 DP8 0 ...

Page 199

... Accesses to $4000–$7FFF will be mapped to $14_4000-$14_7FFF in the global memory space (external access). 1 Accesses to $4000–$7FFF will be mapped to $0F_C000-$0F_FFFF in the global memory space (RAM area). Freescale Semiconductor ;many cases assemblers are “direct page aware” and can ;automatically select direct mode. ...

Page 200

... MC9S12XE-Family Reference Manual Rev. 1.25 Table Table 3-12) (1) (2) DATA SOURCE Stretch Internal Flash N Emulation Memory N Internal Flash External Application Y Internal Flash N External Application Y Emulation Memory N Internal Flash External Application N Internal Flash Freescale Semiconductor 3-12) ...