S912XET512J3VALR Freescale Semiconductor, S912XET512J3VALR Datasheet - Page 344

• Manufacturer Part Number: S912XET512J3VALR
• Description: 16-bit Microcontrollers - MCU 16 BIT,512K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S912XET512J3VALR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12XE
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-112
• Mounting Style: SMD/SMT

Chapter 8 S12X Debug (S12XDBGV3) Module
8.4.7.3
If a TRIG triggers occur, the Final State is entered. If a tracing session is selected by TSOURCE,
breakpoints are requested when the tracing session has completed, thus if Begin or Mid aligned triggering
is selected, the breakpoint is requested only on completion of the subsequent trace (see
tracing session is selected, breakpoints are requested immediately. TRIG breakpoints are possible even if
the S12XDBG module is disarmed.
8.4.7.4
Tagging using the external TAGHI/TAGLO pins always ends the session immediately at the tag hit. It is
always end aligned, independent of internal channel trigger alignment configuration.
8.4.7.5
XGATE software breakpoints have the highest priority. Active tracing sessions are terminated
immediately.
If a TRIG trigger occurs after Begin or Mid aligned tracing has already been triggered by a comparator
instigated transition to Final State, then TRIG no longer has an effect. When the associated tracing session
is complete, the breakpoint occurs. Similarly if a TRIG is followed by a subsequent trigger from a
comparator channel, it has no effect, since tracing has already started.
If a comparator tag hit occurs simultaneously with an external TAGHI/TAGLO hit, the state sequencer
enters state0. TAGHI/TAGLO triggers are always end aligned, to end tracing immediately, independent of
the tracing trigger alignment bits TALIGN[1:0].
8.4.7.5.1
Breakpoint operation is dependent on the state of the S12XBDM module. If the S12XBDM module is
active, the CPU12X is executing out of BDM firmware and S12X breakpoints are disabled. In addition,
while executing a BDM TRACE command, tagging into BDM is disabled. If BDM is not active, the
breakpoint will give priority to BDM requests over SWI requests if the breakpoint coincides with a SWI
instruction in the user’s code. On returning from BDM, the SWI from user code gets executed.
BDM cannot be entered from a breakpoint unless the ENABLE bit is set in the BDM. If entry to BDM via
a BGND instruction is attempted and the ENABLE bit in the BDM is cleared, the CPU12X actually
344
DBGBRK[1]
(DBGC1[3])
Breakpoints Generated Via The TRIG Bit
Breakpoints Via TAGHI Or TAGLO Pin Taghits
S12XDBG Breakpoint Priorities
S12XDBG Breakpoint Priorities And BDM Interfacing
0
1
1
1
1
1
(DBGC1[4])
MC9S12XE-Family Reference Manual Rev. 1.25
Table 8-49. Breakpoint Mapping Summary
BDM Bit
X
0
0
1
1
1
Enabled
BDM
X
X
X
0
1
1
Active
BDM
X
X
0
1
0
1
Breakpoint to BDM
Breakpoint to SWI
Breakpoint to SWI
S12X Breakpoint
No Breakpoint
No Breakpoint
No Breakpoint
Mapping
Freescale Semiconductor
Table
8-48). If no