S912XET512J3VALR Freescale Semiconductor, S912XET512J3VALR Datasheet - Page 293

• Manufacturer Part Number: S912XET512J3VALR
• Description: 16-bit Microcontrollers - MCU 16 BIT,512K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S912XET512J3VALR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12XE
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-112
• Mounting Style: SMD/SMT

7.4.6
The BDM communicates with external devices serially via the BKGD pin. During reset, this pin is a mode
select input which selects between normal and special modes of operation. After reset, this pin becomes
the dedicated serial interface pin for the BDM.
The BDM serial interface is timed using the clock selected by the CLKSW bit in the status register see
Section 7.3.2.1, “BDM Status Register
the following explanation.
The BDM serial interface uses a clocking scheme in which the external host generates a falling edge on
the BKGD pin to indicate the start of each bit time. This falling edge is sent for every bit whether data is
transmitted or received. Data is transferred most significant bit (MSB) first at 16 target clock cycles per
bit. The interface times out if 512 clock cycles occur between falling edges from the host.
The BKGD pin is a pseudo open-drain pin and has an weak on-chip active pull-up that is enabled at all
times. It is assumed that there is an external pull-up and that drivers connected to BKGD do not typically
drive the high level. Since R-C rise time could be unacceptably long, the target system and host provide
brief driven-high (speedup) pulses to drive BKGD to a logic 1. The source of this speedup pulse is the host
for transmit cases and the target for receive cases.
The timing for host-to-target is shown in
Figure
the host and target are operating from separate clocks, it can take the target system up to one full clock
1. Target clock cycles are cycles measured using the target MCU’s serial clock rate. See
Freescale Semiconductor
and
Section 7.3.2.1, “BDM Status Register (BDMSTS)”
Hardware
Hardware
Firmware
Firmware
TRACE
7-10. All four cases begin when the host drives the BKGD pin low to generate a falling edge. Since
Read
Read
Write
Write
GO,
BDM Serial Interface
AT ~16 TC/Bit
Command
Command
Command
Command
Command
8 Bits
DELAY
48-BC
76-BC
Delay
MC9S12XE-Family Reference Manual Rev. 1.25
AT ~16 TC/Bit
Figure 7-7. BDM Command Structure
Address
Address
16 Bits
Data
Command
(BDMSTS)”. This clock will be referred to as the target clock in
Next
Data
Figure 7-8
for information on how serial clock rate is selected.
DELAY
36-BC
and that of target-to-host in
150-BC
Delay
Command
Command
Next
Next
Data
Chapter 7 Background Debug Module (S12XBDMV2)
AT ~16 TC/Bit
16 Bits
Data
BC = Bus Clock Cycles
TC = Target Clock Cycles
Section 7.4.6, “BDM Serial Interface”
150-BC
Delay
Figure 7-9
Command
Command
Next
Next
and
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