S912XET512J3VALR Freescale Semiconductor, S912XET512J3VALR Datasheet - Page 308

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S912XET512J3VALR

Manufacturer Part Number
S912XET512J3VALR
Description
16-bit Microcontrollers - MCU 16 BIT,512K FLASH
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S912XET512J3VALR

Rohs
yes
Core
HCS12X
Processor Series
MC9S12XE
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
512 KB
Data Ram Size
32 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-112
Mounting Style
SMD/SMT

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
S912XET512J3VALR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Chapter 8 S12X Debug (S12XDBGV3) Module
8.1.5
8.2
The S12XDBG sub-module features two external tag input signals. See Device User Guide (DUG) for the
mapping of these signals to device pins. These tag pins may be used for the external tagging in emulation
modes only.
8.3
8.3.1
A summary of the registers associated with the S12XDBG sub-block is shown in
descriptions of the registers and bits are given in the subsections that follow.
308
(See DUG)
(See DUG)
(See DUG)
Pin Name
TAGHITS
EXTERNAL TAGHI / TAGLO
XGATE S/W BREAKPOINT REQUEST
SECURE
CPU12X BUS
XGATE BUS
TAGLO
TAGLO
TAGHI
READ TRACE DATA (DBG READ DATA BUS)
External Signal Description
Memory Map and Registers
Block Diagram
Module Memory Map
Tagging Enable
Pin Functions
Unconditional
Table 8-4. External System Pins Associated With S12XDBG
TAGLO
TAGHI
COMPARATOR A
COMPARATOR B
COMPARATOR C
COMPARATOR D
MC9S12XE-Family Reference Manual Rev. 1.25
Figure 8-1. Debug Module Block Diagram
When instruction tagging is on, tags the high half of the instruction word being
read into the instruction queue.
When instruction tagging is on, tags the low half of the instruction word being
read into the instruction queue.
In emulation modes, a low assertion on this pin in the 7th or 8th cycle after the
end of reset enables the Unconditional Tagging function.
MATCH0
MATCH1
MATCH2
MATCH3
CONTROL
TRIGGER
LOGIC
TAG &
Description
TRIGGER
STATE
BREAKPOINT REQUESTS
CPU12X & XGATE
STATE SEQUENCER
Table
TRACE BUFFER
TAGS
Freescale Semiconductor
STATE
8-2. Detailed
TRACE
CONTROL
TRIGGER

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