S912XET512J3VALR Freescale Semiconductor, S912XET512J3VALR Datasheet - Page 803

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S912XET512J3VALR

Manufacturer Part Number
S912XET512J3VALR
Description
16-bit Microcontrollers - MCU 16 BIT,512K FLASH
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S912XET512J3VALR

Rohs
yes
Core
HCS12X
Processor Series
MC9S12XE
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
512 KB
Data Ram Size
32 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-112
Mounting Style
SMD/SMT

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S912XET512J3VALR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
22.3.2.12 Main Timer Interrupt Flag 1 (TFLG1)
Read: Anytime
Write: Used in the clearing mechanism (set bits cause corresponding bits to be cleared). Writing a zero
will not affect current status of the bit.
22.3.2.13 Main Timer Interrupt Flag 2 (TFLG2)
TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write the bit
to one while TEN bit of TSCR1 or PAEN bit of PACTL is set to one.
Read: Anytime
Write: Used in clearing mechanism (set bits cause corresponding bits to be cleared).
Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set.
Freescale Semiconductor
Module Base + 0x000E
Module Base + 0x000F
C[7:0]F
Reset
Reset
Field
7:0
W
W
R
R
Input Capture/Output Compare Channel “x” Flag — These flags are set when an input capture or output
compare event occurs. Clearing requires writing a one to the corresponding flag bit while TEN or PAEN is set to
one.
When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare channel
(0x0010–0x001F) will cause the corresponding channel flag CxF to be cleared.
TOF
C7F
0
0
7
7
The newly selected prescale factor will not take effect until the next
synchronized edge where all prescale counter stages equal zero.
Unimplemented or Reserved
C6F
0
0
0
6
6
Figure 22-20. Main Timer Interrupt Flag 1 (TFLG1)
Figure 22-21. Main Timer Interrupt Flag 2 (TFLG2)
MC9S12XE-Family Reference Manual Rev. 1.25
Table 22-16. TRLG1 Field Descriptions
C5F
0
0
0
5
5
C4F
NOTE
0
0
0
4
4
Description
Chapter 22 Timer Module (TIM16B8CV2) Block Description
C3F
0
0
0
3
3
C2F
0
0
0
2
2
C1F
0
0
0
1
1
C0F
0
0
0
0
0
803

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