S912XET512J3VALR Freescale Semiconductor, S912XET512J3VALR Datasheet - Page 288

• Manufacturer Part Number: S912XET512J3VALR
• Description: 16-bit Microcontrollers - MCU 16 BIT,512K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S912XET512J3VALR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12XE
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-112
• Mounting Style: SMD/SMT

Chapter 7 Background Debug Module (S12XBDMV2)
7.4.1
If the user resets into special single chip mode with the system secured, a secured mode BDM firmware
lookup table is brought into the map overlapping a portion of the standard BDM firmware lookup table.
The secure BDM firmware verifies that the on-chip non-volatile memory (e.g. EEPROM and Flash
EEPROM) is erased. This being the case, the UNSEC and ENBDM bit will get set. The BDM program
jumps to the start of the standard BDM firmware and the secured mode BDM firmware is turned off and
all BDM commands are allowed. If the non-volatile memory does not verify as erased, the BDM firmware
sets the ENBDM bit, without asserting UNSEC, and the firmware enters a loop. This causes the BDM
hardware commands to become enabled, but does not enable the firmware commands. This allows the
BDM hardware to be used to erase the non-volatile memory.
BDM operation is not possible in any other mode than special single chip mode when the device is secured.
The device can be unsecured via BDM serial interface in special single chip mode only. More information
regarding security is provided in the security section of the device documentation.
7.4.2
The system must be in active BDM to execute standard BDM firmware commands. BDM can be activated
only after being enabled. BDM is enabled by setting the ENBDM bit in the BDM status (BDMSTS)
register. The ENBDM bit is set by writing to the BDM status (BDMSTS) register, via the single-wire
interface, using a hardware command such as WRITE_BD_BYTE.
After being enabled, BDM is activated by one of the following
When BDM is activated, the CPU finishes executing the current instruction and then begins executing the
firmware in the standard BDM firmware lookup table. When BDM is activated by a breakpoint, the type
of breakpoint used determines if BDM becomes active before or after execution of the next instruction.
In active BDM, the BDM registers and standard BDM firmware lookup table are mapped to addresses
0x7FFF00 to 0x7FFFFF. BDM registers are mapped to addresses 0x7FFF00 to 0x7FFF0B. The BDM uses
these registers which are readable anytime by the BDM. However, these registers are not readable by user
programs.
1. BDM is enabled and active immediately out of special single-chip reset.
2. This method is provided by the S12X_DBG module.
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Hardware BACKGROUND command
CPU BGND instruction
External instruction tagging mechanism
Breakpoint force or tag mechanism
Security
Enabling and Activating BDM
If an attempt is made to activate BDM before being enabled, the CPU
resumes normal instruction execution after a brief delay. If BDM is not
enabled, any hardware BACKGROUND commands issued are ignored by
the BDM and the CPU is not delayed.
MC9S12XE-Family Reference Manual Rev. 1.25
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Freescale Semiconductor