S912XET512J3VALR Freescale Semiconductor, S912XET512J3VALR Datasheet - Page 907

• Manufacturer Part Number: S912XET512J3VALR
• Description: 16-bit Microcontrollers - MCU 16 BIT,512K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S912XET512J3VALR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12XE
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-112
• Mounting Style: SMD/SMT

25.3.2.5
The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array
read access from the CPU or XGATE.
CCIE, IGNSF, FDFD, and FSFD bits are readable and writable while remaining bits read 0 and are not
writable.
Freescale Semiconductor
ECCRIX[2:0]
Offset Module Base + 0x0004
Reset
IGNSF
Field
Field
CCIE
2-0
7
4
W
R
CCIE
ECC Error Register Index— The ECCRIX bits are used to select which word of the FECCR register array is
being read. See
Command Complete Interrupt Enable — The CCIE bit controls interrupt generation when a Flash command
has completed.
0 Command complete interrupt disabled
1 An interrupt will be requested whenever the CCIF flag in the FSTAT register is set (see
Ignore Single Bit Fault — The IGNSF controls single bit fault reporting in the FERSTAT register (see
Section
0 All single bit faults detected during array reads are reported
1 Single bit faults detected during array reads are not reported and the single bit fault interrupt will not be
Flash Configuration Register (FCNFG)
0
7
generated
25.3.2.8).
= Unimplemented or Reserved
0
0
6
Section 25.3.2.13, “Flash ECC Error Results Register
Figure 25-9. Flash Configuration Register (FCNFG)
MC9S12XE-Family Reference Manual Rev. 1.25
Table 25-14. FECCRIX Field Descriptions
Table 25-15. FCNFG Field Descriptions
0
0
5
IGNSF
0
4
Description
Description
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1)
0
0
3
(FECCR),” for more details.
0
0
2
FDFD
0
1
Section
25.3.2.7)
FSFD
0
0
907