S912XET512J3VALR Freescale Semiconductor, S912XET512J3VALR Datasheet - Page 483

• Manufacturer Part Number: S912XET512J3VALR
• Description: 16-bit Microcontrollers - MCU 16 BIT,512K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S912XET512J3VALR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12XE
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-112
• Mounting Style: SMD/SMT

The COP time-out period is restarted if one these two conditions is true:
Freescale Semiconductor
WRTMASK
RSBCK
CR[2:0]
WCOP
1. Writing a non zero value to CR[2:0] (anytime in special modes, once in all other modes) with
2. Changing RSBCK bit from “0” to “1”.
Field
2–0
7
6
5
WRTMASK = 0.
Window COP Mode Bit — When set, a write to the ARMCOP register must occur in the last 25% of the selected
period. A write during the first 75% of the selected period will reset the part. As long as all writes occur during
this window, $55 can be written as often as desired. Once $AA is written after the $55, the time-out logic restarts
and the user must wait until the next window before writing to ARMCOP.
window for the seven available COP rates.
0 Normal COP operation
1 Window COP operation
COP and RTI Stop in Active BDM Mode Bit
0 Allows the COP and RTI to keep running in Active BDM mode.
1 Stops the COP and RTI counters whenever the part is in Active BDM mode.
Write Mask for WCOP and CR[2:0] Bit — This write-only bit serves as a mask for the WCOP and CR[2:0] bits
while writing the COPCTL register. It is intended for BDM writing the RSBCK without touching the contents of
WCOP and CR[2:0].
0 Write of WCOP and CR[2:0] has an effect with this write of COPCTL
1 Write of WCOP and CR[2:0] has no effect with this write of COPCTL.
COP Watchdog Timer Rate Select — These bits select the COP time-out rate (see
nonzero value to CR[2:0] enables the COP counter and starts the time-out period. A COP counter time-out
causes a system reset. This can be avoided by periodically (before time-out) reinitialize the COP counter via the
ARMCOP register.
While all of the following four conditions are true the CR[2:0], WCOP bits are ignored and the COP operates at
highest time-out period (
or
(Does not count for “write once”.)
1) COP is enabled (CR[2:0] is not 000)
2) BDM mode active
3) RSBCK = 0
4) Operation in emulation or special modes
CR2
0
0
0
0
1
1
1
MC9S12XE-Family Reference Manual Rev. 1.25
Table 11-12. COPCTL Field Descriptions
2
24
Table 11-13. COP Watchdog Rates
CR1
cycles) in normal COP mode (Window COP mode disabled):
0
0
1
1
0
0
1
CR0
0
1
0
1
0
1
0
Description
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
Cycles to Timeout
COP disabled
OSCCLK
2
2
2
2
2
2
14
16
18
20
22
23
(1)
Table 11-13
shows the duration of this
Table
11-13). Writing a
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