S912XET512J3VALR Freescale Semiconductor, S912XET512J3VALR Datasheet - Page 819

• Manufacturer Part Number: S912XET512J3VALR
• Description: 16-bit Microcontrollers - MCU 16 BIT,512K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S912XET512J3VALR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12XE
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-112
• Mounting Style: SMD/SMT

23.2.4
Signals VDDF/VSS are the secondary outputs of VREG_3V3 that provide the power supply for the NVM
logic. These signals are connected to device pins to allow external decoupling capacitors (220 nF, X7R
ceramic).
In Shutdown Mode an external supply driving VDDF/VSS can replace the voltage regulator.
23.2.5
Signals VDDPLL/VSSPLL are the secondary outputs of VREG_3V3 that provide the power supply for
the PLL and oscillator. These signals are connected to device pins to allow external decoupling capacitors
(100 nF...220 nF, X7R ceramic).
In Shutdown Mode, an external supply driving VDDPLL/VSSPLL can replace the voltage regulator.
23.2.6
Signals VDDX/VSS are monitored by VREG_3V3 with the LVR feature.
23.2.7
This optional signal is used to shutdown VREG_3V3. In that case, VDD/VSS and VDDPLL/VSSPLL
must be provided externally. Shutdown mode is entered with VREGEN being low. If VREGEN is high,
the VREG_3V3 is either in Full Performance Mode or in Reduced Power Mode.
For the connectivity of VREGEN, see device specification.
23.2.8
This pin provides the signal selected via APIEA if system is set accordingly. See
Periodical Interrupt Control Register (VREGAPICL)
for details.
For the connectivity of VREG_API, see device specification.
23.3
This section provides a detailed description of all registers accessible in VREG_3V3.
If enabled in the system, the VREG_3V3 will abort all read and write accesses to reserved registers within
it’s memory slice. See device level specification for details.
Freescale Semiconductor
Memory Map and Register Definition
VDDF — Regulator Output2 (NVM Logic) Pins
VDDPLL, VSSPLL — Regulator Output3 (PLL) Pins
VDDX — Power Input Pin
VREGEN — Optional Regulator Enable Pin
VREG_API — Optional Autonomous Periodical Interrupt Output Pin
is not supported while MCU is powered.
Switching from FPM or RPM to shutdown of VREG_3V3 and vice versa
MC9S12XE-Family Reference Manual Rev. 1.25
NOTE
and
23.4.8, “Autonomous Periodical Interrupt (API)
Chapter 23 Voltage Regulator (S12VREGL3V3V1)
23.3.2.3, “Autonomous
819