S912XET512J3VALR Freescale Semiconductor, S912XET512J3VALR Datasheet - Page 887

• Manufacturer Part Number: S912XET512J3VALR
• Description: 16-bit Microcontrollers - MCU 16 BIT,512K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S912XET512J3VALR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12XE
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-112
• Mounting Style: SMD/SMT

24.4.3
The Flash module can generate an interrupt when a Flash command operation has completed or when a
Flash command operation has detected an EEE error or an ECC fault.
24.4.3.1
The Flash module uses the CCIF flag in combination with the CCIE interrupt enable bit to generate the
Flash command interrupt request. The Flash module uses the ERSEIF, PGMEIF, EPVIOLIF, ERSVIF1,
ERSVIF0, DFDIF and SFDIF flags in combination with the ERSEIE, PGMEIE, EPVIOLIE, ERSVIE1,
ERSVIE0, DFDIE and SFDIE interrupt enable bits to generate the Flash error interrupt request. For a
detailed description of the register bits involved, refer to
(FCNFG)”,
Status Register
The logic used for generating the Flash module interrupts is shown in
Freescale Semiconductor
Flash Command Complete
Flash EEE Erase Error
Flash EEE Program Error
Flash EEE Protection Violation
Flash EEE Error Type 1 Violation
Flash EEE Error Type 0 Violation
ECC Double Bit Fault on Flash Read
ECC Single Bit Fault on Flash Read
Section 24.3.2.6, “Flash Error Configuration Register
Interrupts
Description of Flash Interrupt Operation
Vector addresses and their relative interrupt priority are determined at the
MCU level.
(FSTAT)”, and
Interrupt Source
MC9S12XE-Family Reference Manual Rev. 1.25
Section 24.3.2.8, “Flash Error Status Register
Table 24-77. Flash Interrupt Sources
(FERSTAT register)
(FERSTAT register)
(FERSTAT register)
(FERSTAT register)
(FERSTAT register)
(FERSTAT register)
(FERSTAT register)
(FSTAT register)
Interrupt Flag
PGMERIF
EPVIOLIF
ERSERIF
ERSVIF1
ERSVIF0
DFDIF
SFDIF
CCIF
NOTE
Section 24.3.2.5, “Flash Configuration Register
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1)
(FERCNFG register)
(FERCNFG register)
(FERCNFG register)
(FERCNFG register)
(FERCNFG register)
(FERCNFG register)
(FERCNFG register)
(FCNFG register)
(FERCNFG)”,
Local Enable
PGMERIE
EPVIOLIE
ERSERIE
ERSVIE1
ERSVIE0
DFDIE
SFDIE
CCIE
Figure
24-27.
(FERSTAT)”.
Section 24.3.2.7, “Flash
Global (CCR)
Mask
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
887