S912XET512J3VALR Freescale Semiconductor, S912XET512J3VALR Datasheet - Page 171

• Manufacturer Part Number: S912XET512J3VALR
• Description: 16-bit Microcontrollers - MCU 16 BIT,512K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S912XET512J3VALR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12XE
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-112
• Mounting Style: SMD/SMT

1. Read: Anytime.
1. Read: Anytime.
2.3.96
2.3.97
Freescale Semiconductor
Address 0x0373
Address 0x0374
Write: Anytime.
Write: Anytime.
RDRL
PERL
Field
Field
Reset
Reset
7-0
7-0
W
W
R
R
Port L reduced drive—Select reduced drive for outputs
This register configures the drive strength of output pins 7 through 0 as either full or reduced independent of the
function used on the pins. If a pin is used as input this bit has no effect.
1 Reduced drive selected (approx. 1/5 of the full drive strength).
0 Full drive strength enabled.
Port L pull device enable—Enable pull devices on input pins
These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect
if the pin is used as an output. Out of reset all pull devices are enabled.
1 Pull device enabled.
0 Pull device disabled.
RDRL7
PERL7
Port L Reduced Drive Register (RDRL)
Port L Pull Device Enable Register (PERL)
0
1
7
7
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTL or PTIL registers, when changing the
DDRL register.
RDRL6
PERL6
Figure 2-95. Port L Pull Device Enable Register (PERL)
0
1
6
6
Figure 2-94. Port L Reduced Drive Register (RDRL)
Table 2-91. RDRL Register Field Descriptions
Table 2-92. PERL Register Field Descriptions
MC9S12XE-Family Reference Manual Rev. 1.25
RDRL5
PERL5
0
1
5
5
RDRL4
PERL4
NOTE
0
1
4
4
Description
Description
RDRL3
PERL3
3
0
3
1
Chapter 2 Port Integration Module (S12XEPIMV1)
RDRL2
PERL2
0
1
2
2
Access: User read/write
Access: User read/write
RDRL1
PERL1
0
1
1
1
RDRL0
PERL0
0
1
0
0
171
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