S912XET512J3VALR Freescale Semiconductor, S912XET512J3VALR Datasheet - Page 261

• Manufacturer Part Number: S912XET512J3VALR
• Description: 16-bit Microcontrollers - MCU 16 BIT,512K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S912XET512J3VALR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12XE
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-112
• Mounting Style: SMD/SMT

Chapter 6
Interrupt (S12XINTV2)
6.1
The XINT module decodes the priority of all system exception requests and provides the applicable vector
for processing the exception to either the CPU or the XGATE module. The XINT module supports:
Each of the I bit maskable interrupt requests can be assigned to one of seven priority levels supporting a
flexible priority scheme. For interrupt requests that are configured to be handled by the CPU, the priority
scheme can be used to implement nested interrupt capability where interrupts from a lower level are
automatically blocked if a higher level interrupt is being processed. Interrupt requests configured to be
handled by the XGATE module can be nested one level deep.
Freescale Semiconductor
Revision
Number
V02.00
V02.04
V02.05
V02.07
•
•
•
•
•
•
•
I bit and X bit maskable interrupt requests
One non-maskable unimplemented op-code trap
One non-maskable software interrupt (SWI) or background debug mode request
One non-maskable system call interrupt (SYS)
Three non-maskable access violation interrupts
One spurious interrupt vector request
Three system reset vector requests
Introduction
Revision Date
13 Dec 2011
20 Mar 2007
11 Jan 2007
01 Jul 2005
The HPRIO register and functionality of the original S12 interrupt module
is no longer supported. It is superseded by the 7-level interrupt request
priority scheme.
6.3.2.2/6-267
6.3.2.4/6-268
6.5.3.1/6-276
6.1.2/6-262
6.4.6/6-274
Sections
Affected
MC9S12XE-Family Reference Manual Rev. 1.25
Table 6-1. Revision History
Initial V2 release, added new features:
- XGATE threads can be interrupted.
- SYS instruction vector.
- Access violation interrupt vectors.
- Added Notes for devices without XGATE module.
- Fixed priority definition for software exceptions.
- Re-worded for difference of Wake-up feature between STOP and WAIT
modes.
NOTE
Description of Changes
261