S912XET512J3VALR Freescale Semiconductor, S912XET512J3VALR Datasheet - Page 382

• Manufacturer Part Number: S912XET512J3VALR
• Description: 16-bit Microcontrollers - MCU 16 BIT,512K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S912XET512J3VALR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12XE
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-112
• Mounting Style: SMD/SMT

Chapter 10 XGATE (S12XGATEV3)
10.8
10.8.1
For the ease of implementation the architecture is a strict Load/Store RISC machine, which means all
operations must have one of the eight general purpose registers R0 … R7 as their source as well their
destination.
All word accesses must work with a word aligned address, that is A[0] = 0!
10.8.1.1
10.8.1.2
Instructions that use this addressing mode either have no operands or all operands are in internal XGATE
registers.
Examples:
382
RD
RD.L
RD.H
RS, RS1, RS2
RS.L, RS1.L, RS2.L
RS.H, RS1.H, RS2.H
RB
RI
RI+
–RI
Instruction Set
BRK
RTS
Addressing Modes
Naming Conventions
Inherent Addressing Mode (INH)
Even though register R1 is intended to be used as a pointer to the data
segment, it may be used as a general purpose data register as well.
Selecting R0 as destination register will discard the result of the instruction.
Only the condition code register will be updated
MC9S12XE-Family Reference Manual Rev. 1.25
Destination register, allowed range is R0–R7
Low byte of the destination register, bits [7:0]
High byte of the destination register, bits [15:8]
Source register, allowed range is R0–R7
Low byte of the source register, bits [7:0]
High byte of the source register, bits[15:8]
Base register for indexed addressing modes, allowed
range is R0–R7
Offset register for indexed addressing modes with
register offset, allowed range is R0–R7
Offset register for indexed addressing modes with
register offset and post-increment,
Allowed range is R0–R7 (R0+ is equivalent to R0)
Offset register for indexed addressing modes with
register offset and pre-decrement,
Allowed range is R0–R7 (–R0 is equivalent to R0)
NOTE
Freescale Semiconductor