S912XET512J3VALR Freescale Semiconductor, S912XET512J3VALR Datasheet - Page 707

• Manufacturer Part Number: S912XET512J3VALR
• Description: 16-bit Microcontrollers - MCU 16 BIT,512K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S912XET512J3VALR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12XE
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-112
• Mounting Style: SMD/SMT

19.3.2.14 PWM Channel Duty Registers (PWMDTYx)
There is a dedicated duty register for each channel. The value in this register determines the duty of the
associated PWM channel. The duty value is compared to the counter and if it is equal to the counter value
a match occurs and the output changes state.
The duty registers for each channel are double buffered so that if they change while the channel is enabled,
the change will NOT take effect until one of the following occurs:
In this way, the output of the PWM will always be either the old duty waveform or the new duty waveform,
not some variation in between. If the channel is not enabled, then writes to the duty register will go directly
to the latches as well as the buffer.
See
To calculate the output duty cycle (high time as a% of period) for a particular channel:
For boundary case programming values, please refer to
Read: Anytime
Freescale Semiconductor
Module Base + 0x001C = PWMDTY0, 0x001D = PWMDTY1, 0x001E = PWMDTY2, 0x001F = PWMDTY3
Module Base + 0x0020 = PWMDTY4, 0x0021 = PWMDTY5, 0x0022 = PWMDTY6, 0x0023 = PWMDTY7
Reset
•
•
•
•
•
Section 19.4.2.3, “PWM Period and Duty”
W
R
The effective period ends
The counter is written (counter resets to $00)
The channel is disabled
Polarity = 0 (PPOL x =0)
Polarity = 1 (PPOLx = 1)
Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100%
Duty Cycle = [PWMDTYx / PWMPERx] * 100%
Bit 7
1
7
Reads of this register return the most recent value written. Reads do not
necessarily return the value of the currently active duty due to the double
buffering scheme.
Depending on the polarity bit, the duty registers will contain the count of
either the high time or the low time. If the polarity bit is one, the output starts
high and then goes low when the duty count is reached, so the duty registers
contain a count of the high time. If the polarity bit is zero, the output starts
low and then goes high when the duty count is reached, so the duty registers
contain a count of the low time.
Figure 19-16. PWM Channel Duty Registers (PWMDTYx)
1
6
6
MC9S12XE-Family Reference Manual Rev. 1.25
1
5
5
for more information.
NOTE
NOTE
1
4
4
Section 19.4.2.8, “PWM Boundary
1
3
3
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1)
1
2
2
1
1
1
Cases”.
Bit 0
1
0
707