S912XET512J3VALR Freescale Semiconductor, S912XET512J3VALR Datasheet - Page 550

• Manufacturer Part Number: S912XET512J3VALR
• Description: 16-bit Microcontrollers - MCU 16 BIT,512K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S912XET512J3VALR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12XE
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-112
• Mounting Style: SMD/SMT

Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
550
.
CLK[1:0]
PEDGE
PAOVI
Field
PAI
3:2
4
2
0
Pulse Accumulator Edge Control — This bit is active only when the Pulse Accumulator A is enabled
(PAEN = 1). Refer to
For PAMOD bit = 0 (event counter mode).
0 Falling edges on IC7 pin cause the count to be incremented
1 Rising edges on IC7 pin cause the count to be incremented
For PAMOD bit = 1 (gated time accumulation mode).
0 IC7 input pin high enables bus clock divided by 64 to Pulse Accumulator and the trailing falling edge on IC7
1 IC7 input pin low enables bus clock divided by 64 to Pulse Accumulator and the trailing rising edge on IC7 sets
If the timer is not active (TEN = 0 in TSCR1), there is no divide-by-64 since the ÷64 clock is generated by the
timer prescaler.
Clock Select Bits — For the description of PACLK please refer to
If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always used as an input
clock to the timer counter. The change from one selected clock to the other happens immediately after these bits
are written. Refer to
Pulse Accumulator A Overflow Interrupt Enable
0 Interrupt inhibited
1 Interrupt requested if PAOVF is set
Pulse Accumulator Input Interrupt Enable
0 Interrupt inhibited
1 Interrupt requested if PAIF is set
sets the PAIF flag.
the PAIF flag.
PAMOD
CLK1
0
0
1
1
0
0
1
1
Table 14-19. PACTL Field Descriptions (continued)
Table
Table
PEDGE
CLK0
MC9S12XE-Family Reference Manual Rev. 1.25
0
1
0
1
0
1
0
1
14-21.
14-20.
Table 14-21. Clock Selection
Falling edge
Rising edge
Divide by 64 clock enabled with pin high level
Divide by 64 clock enabled with pin low level
Use timer prescaler clock as timer counter clock
Use PACLK as input to timer counter clock
Use PACLK/256 as timer counter clock frequency
Use PACLK/65536 as timer counter clock frequency
Table 14-20. Pin Action
Description
Clock Source
Pin Action
Figure
14-72.
Freescale Semiconductor