S912XET512J3VALR Freescale Semiconductor, S912XET512J3VALR Datasheet - Page 227

• Manufacturer Part Number: S912XET512J3VALR
• Description: 16-bit Microcontrollers - MCU 16 BIT,512K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S912XET512J3VALR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12XE
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-112
• Mounting Style: SMD/SMT

Chapter 4
Memory Protection Unit (S12XMPUV1)
4.1
The MPU module provides basic functionality required to protect memory mapped resources from
undesired accesses. Multiple address range comparators compare memory accesses against eight memory
protection descriptors located in the MPU module to determine if each access is valid or not. The
comparison is sensitive to which bus master generates the access and the type of the access.
The MPU module can be used to isolate memory ranges accessible by different bus masters. It can be also
be used by an operating system or software kernel to isolate the regions of memory “legally” available to
specific software tasks, with the kernel re-configuring the task specific memory protection descriptors in
supervisor state during task-switching.
4.1.1
The following terms and abbreviations are used in the document.
4.1.2
The MPU module monitors the bus activity of each bus master. The data describing each access is fed into
multiple address range comparators. The output of the comparators is used to determine if a particular
Freescale Semiconductor
Revision
Number
V01.04
V01.05
V01.06
Introduction
supervisor state
Revision Date
14 Sep 2005
Preface
Overview
14 Mar 2006
09 Oct 2006
user state
XGATE
Term
MCU
MPU
CPU
4.3.1.1/4-231
4.3.1.1/4-231
4.4.1/4-237
Micro-Controller Unit
Memory Protection Unit
S12X Central Processing Unit (see S12XCPU Reference Manual)
XGATE Co-processor (see XGATE chapter)
refers to the supervisor state of the S12XCPU (see S12XCPU Reference Manual)
refers to the user state of the S12XCPU (see S12XCPU Reference Manual)
Sections
4.4/4-237
Affected
MC9S12XE-Family Reference Manual Rev. 1.25
Table 4-1. Revision History
- Added note to only use the CPU to clear the AE flag.
- Added disclaimer to avoid changing descriptors while they are in use
because of other bus-masters doing accesses.
- Clarified that interrupt generation is independent of AEF bit state.
- Corrected preliminary statement about execution of violating accesses.
- Made Revision History entries public.
Table 4-2. Terminology
Meaning
Description of Changes
227