S912XET512J3VALR Freescale Semiconductor, S912XET512J3VALR Datasheet - Page 611

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S912XET512J3VALR

Manufacturer Part Number
S912XET512J3VALR
Description
16-bit Microcontrollers - MCU 16 BIT,512K FLASH
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S912XET512J3VALR

Rohs
yes
Core
HCS12X
Processor Series
MC9S12XE
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
512 KB
Data Ram Size
32 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-112
Mounting Style
SMD/SMT

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S912XET512J3VALR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
16.3.2
This section describes in detail all the registers and register bits in the MSCAN module. Each description
includes a standard register diagram with an associated figure number. Details of register bit and field
function follow the register diagrams, in bit order. All bits of all registers in this module are completely
synchronous to internal clocks during a register read.
16.3.2.1
The CANCTL0 register provides various control bits of the MSCAN module as described below.
Freescale Semiconductor
Module Base + 0x0000
0x001C–0x001F
0x0018–0x001B
0x0020–0x002F
0x0030–0x003F
0x0010–0x0013
0x0014–0x0017
CANIDMR4–7
CANIDAR0–3
CANIDAR4–7
CANTXERR
CANIDMRx
CANRXFG
CANTXFG
Register
0x000F
Reset:
Name
W
R
Register Descriptions
MSCAN Control Register 0 (CANCTL0)
RXFRM
0
7
R
W
R
W
R
W
R
W
R
W
R
W
R
W
TXERR7
Bit 7
AM7
AM7
AC7
AC7
= Unimplemented
RXACT
Figure 16-3. MSCAN Register Summary (continued)
Figure 16-4. MSCAN Control Register 0 (CANCTL0)
6
0
MC9S12XE-Family Reference Manual Rev. 1.25
= Unimplemented or Reserved
TXERR6
AM6
AM6
AC6
AC6
6
See
See
CSWAI
Section 16.3.3, “Programmer’s Model of Message
Section 16.3.3, “Programmer’s Model of Message
0
5
TXERR5
AM5
AM5
AC5
AC5
5
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3)
SYNCH
4
0
TXERR4
AM4
AM4
AC4
AC4
4
TIME
0
3
TXERR3
AM3
AM3
AC3
AC3
3
WUPE
TXERR2
2
0
AM2
AM2
AC2
AC2
2
Storage”
Storage”
Access: User read/write
SLPRQ
TXERR1
0
1
AM1
AM1
AC1
AC1
1
INITRQ
TXERR0
Bit 0
AM0
AM0
AC0
AC0
0
1
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