S912XET512J3VALR Freescale Semiconductor, S912XET512J3VALR Datasheet - Page 618

• Manufacturer Part Number: S912XET512J3VALR
• Description: 16-bit Microcontrollers - MCU 16 BIT,512K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S912XET512J3VALR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12XE
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-112
• Mounting Style: SMD/SMT

Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3)
1. Read: Anytime
1. The RSTAT[1:0], TSTAT[1:0] bits are not affected by initialization mode.
618
RSTAT[1:0]
TSTAT[1:0]
Write: Anytime when not in initialization mode, except RSTAT[1:0] and TSTAT[1:0] flags which are read-only; write of 1 clears
flag; write of 0 is ignored
WUPIF
CSCIF
Field
5-4
3-2
7
6
Wake-Up Interrupt Flag — If the MSCAN detects CAN bus activity while in sleep mode (see
“MSCAN Sleep
(CANCTL0)”), the module will set WUPIF. If not masked, a wake-up interrupt is pending while this flag is set.
0 No wake-up activity observed while in sleep mode
1 MSCAN detected activity on the CAN bus and requested wake-up
CAN Status Change Interrupt Flag — This flag is set when the MSCAN changes its current CAN bus status
due to the actual value of the transmit error counter (TEC) and the receive error counter (REC). An additional 4-
bit (RSTAT[1:0], TSTAT[1:0]) status register, which is split into separate sections for TEC/REC, informs the
system on the actual CAN bus status (see
(CANRIER)”). If not masked, an error interrupt is pending while this flag is set. CSCIF provides a blocking
interrupt. That guarantees that the receiver/transmitter status bits (RSTAT/TSTAT) are only updated when no
CAN status change interrupt is pending. If the TECs/RECs change their current value after the CSCIF is
asserted, which would cause an additional state change in the RSTAT/TSTAT bits, these bits keep their status
until the current CSCIF interrupt is cleared again.
0 No change in CAN bus status occurred since last interrupt
1 MSCAN changed current CAN bus status
Receiver Status Bits — The values of the error counters control the actual CAN bus status of the MSCAN. As
soon as the status change interrupt flag (CSCIF) is set, these bits indicate the appropriate receiver related CAN
bus status of the MSCAN. The coding for the bits RSTAT1, RSTAT0 is:
00 RxOK:
01 RxWRN:
10 RxERR:
11 Bus-off
Transmitter Status Bits — The values of the error counters control the actual CAN bus status of the MSCAN.
As soon as the status change interrupt flag (CSCIF) is set, these bits indicate the appropriate transmitter related
CAN bus status of the MSCAN. The coding for the bits TSTAT1, TSTAT0 is:
00 TxOK:
01 TxWRN: 96 ≤ transmit error counter < 128
10 TxERR: 128 ≤ transmit error counter < 256
11 Bus-Off: 256 ≤ transmit error counter
The CANRFLG register is held in the reset state
mode is active (INITRQ = 1 and INITAK = 1). This register is writable again
as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0).
(1)
: 256 ≤ transmit error counter
128 ≤ receive error counter
0 ≤ transmit error counter < 96
96 ≤ receive error counter < 128
Mode,”) and WUPE = 1 in CANTCTL0 (see
0 ≤ receive error counter < 96
Table 16-11. CANRFLG Register Field Descriptions
MC9S12XE-Family Reference Manual Rev. 1.25
Section 16.3.2.6, “MSCAN Receiver Interrupt Enable Register
NOTE
Description
Section 16.3.2.1, “MSCAN Control Register 0
1
when the initialization
Freescale Semiconductor
Section 16.4.5.5,