S912XET512J3VALR Freescale Semiconductor, S912XET512J3VALR Datasheet - Page 28

• Manufacturer Part Number: S912XET512J3VALR
• Description: 16-bit Microcontrollers - MCU 16 BIT,512K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S912XET512J3VALR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12XE
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-112
• Mounting Style: SMD/SMT

Chapter 1 Device Overview MC9S12XE-Family
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16-Bit CPU12X
— Upward compatible with MC9S12 instruction set with the exception of five Fuzzy instructions
— Enhanced indexed addressing
— Access to large data segments independent of PPAGE
INT (interrupt module)
— Eight levels of nested interrupts
— Flexible assignment of interrupt sources to each interrupt level.
— External non-maskable high priority interrupt (XIRQ)
— Internal non-maskable high priority Memory Protection Unit interrupt
— Up to 24 pins on ports J, H and P configurable as rising or falling edge sensitive interrupts
EBI (external bus interface)(available in 208-Pin and 144-Pin packages only)
— Up to four chip select outputs to select 16K, 1M, 2M and up to 4MByte address spaces
— Each chip select output can be configured to complete transaction on either the time-out of one
MMC (module mapping control)
DBG (debug module)
— Monitoring of CPU and/or XGATE busses with tag-type or force-type breakpoint requests
— 64 x 64-bit circular trace buffer captures change-of-flow or memory access information
BDM (background debug mode)
MPU (memory protection unit)
— 8 address regions definable per active program task
— Address range granularity as low as 8-bytes
— No write / No execute Protection Attributes
— Non-maskable interrupt on access violation
XGATE
— Programmable, high performance I/O coprocessor module
— Transfers data to or from all peripherals and RAM without CPU intervention or CPU wait states
— Performs logical, shifts, arithmetic, and bit operations on data
— Can interrupt the HCS12X CPU signalling transfer completion
— Triggers from any hardware module as well as from the CPU possible
— Two interrupt levels to service high priority tasks
— Hardware support for stack pointer initialisation
OSC_LCP (oscillator)
— Low power loop control Pierce oscillator utilizing a 4MHz to 16MHz crystal
— Good noise immunity
— Full-swing Pierce option utilizing a 2MHz to 40MHz crystal
— Transconductance sized for optimum start-up margin for typical crystals
IPLL (Internally filtered, frequency modulated phase-locked-loop clock generation)
(MEM, WAV, WAVR, REV, REVW) which have been removed
of the two wait state generators or the deassertion of EWAIT signal
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor