S912XET512J3VALR Freescale Semiconductor, S912XET512J3VALR Datasheet - Page 337

Manufacturer Part Number

S912XET512J3VALR

16-bit Microcontrollers - MCU 16 BIT,512K FLASH

Manufacturer

Freescale Semiconductor

Processor Series

Data Bus Width

Maximum Clock Frequency

Program Memory Size

Data Ram Size

Operating Supply Voltage

3.13 V to 5.5 V

Operating Temperature Range

- 40 C to + 105 C

Package / Case

Mounting Style

Manufacturer

BOSTOCK HK LIMITED

Part Number:

S912XET512J3VALR

Manufacturer:

Freescale Semiconductor

2 data entries, thus in this case the DBGCNT[0] is incremented after each separate entry. In Detail mode

DBGCNT[0] remains cleared whilst the other DBGCNT bits are incremented on each trace buffer entry.

XGATE and CPU12X COFs occur independently of each other and the proﬁle of COFs for the two sources

is totally different. When both sources are being traced in Normal or Loop1 mode, for each COF from one

source, there may be many COFs from the other source, depending on user code. COF events could occur

far from each other in the time domain, on consecutive cycles or simultaneously. When a COF occurs in

either source (S12X or XGATE) a trace buffer entry is made and the corresponding CDV or XDV bit is

set. The current PC of the other source is simultaneously stored to the trace buffer even if no COF has

occurred, in which case CDV/XDV remains cleared indicating the address is not associated with a COF,

but is simply a snapshot of the PC contents at the time of the COF from the other source.

Single byte data accesses in Detail Mode are always stored to the low byte of the trace buffer (CDATAL

or XDATAL) and the high byte is cleared. When tracing word accesses, the byte at the lower address is

always stored to trace buffer byte3 and the byte at the higher address is stored to byte2.

Freescale Semiconductor

MC9S12XE-Family Reference Manual Rev. 1.25

Table 8-43. Trace Buffer Organization

8-Byte Wide Word Buffer

Chapter 8 S12X Debug (S12XDBGV3) Module