S912XET512J3VALR Freescale Semiconductor, S912XET512J3VALR Datasheet - Page 1157

• Manufacturer Part Number: S912XET512J3VALR
• Description: 16-bit Microcontrollers - MCU 16 BIT,512K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S912XET512J3VALR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12XE
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-112
• Mounting Style: SMD/SMT

29.3.2.6
The FERCNFG register enables the Flash error interrupts for the FERSTAT flags.
All assigned bits in the FERCNFG register are readable and writable.
Freescale Semiconductor
PGMERIE
EPVIOLIE
ERSERIE
Offset Module Base + 0x0005
Reset
FDFD
FSFD
Field
Field
1
0
7
6
4
W
R
ERSERIE
read operations and check the associated interrupt routine. The FDFD bit is cleared by writing a 0 to FDFD. The
FECCR registers will not be updated during the Flash array read operation with FDFD set unless an actual
double bit fault is detected.
0 Flash array read operations will set the DFDIF flag in the FERSTAT register only if a double bit fault is detected
1 Any Flash array read operation will force the DFDIF flag in the FERSTAT register to be set (see
Force Single Bit Fault Detect
read operations and check the associated interrupt routine. The FSFD bit is cleared by writing a 0 to FSFD. The
FECCR registers will not be updated during the Flash array read operation with FSFD set unless an actual single
bit fault is detected.
0 Flash array read operations will set the SFDIF flag in the FERSTAT register only if a single bit fault is detected
1 Flash array read operation will force the SFDIF flag in the FERSTAT register to be set (see
EEE Erase Error Interrupt Enable — The ERSERIE bit controls interrupt generation when a failure is detected
during an EEE erase operation.
0 ERSERIF interrupt disabled
1 An interrupt will be requested whenever the ERSERIF flag is set (see
EEE Program Error Interrupt Enable — The PGMERIE bit controls interrupt generation when a failure is
detected during an EEE program operation.
0 PGMERIF interrupt disabled
1 An interrupt will be requested whenever the PGMERIF flag is set (see
EEE Protection Violation Interrupt Enable — The EPVIOLIE bit controls interrupt generation when a
protection violation is detected during a write to the buffer RAM EEE partition.
0 EPVIOLIF interrupt disabled
1 An interrupt will be requested whenever the EPVIOLIF flag is set (see
Force Double Bit Fault Detect — The FDFD bit allows the user to simulate a double bit fault during Flash array
Flash Error Configuration Register (FERCNFG)
0
7
Section
register is set (see
and an interrupt will be generated as long as the SFDIE interrupt enable in the FERCNFG register is set (see
Section
= Unimplemented or Reserved
29.3.2.7) and an interrupt will be generated as long as the DFDIE interrupt enable in the FERCNFG
29.3.2.6)
PGMERIE
Figure 29-10. Flash Error Configuration Register (FERCNFG)
0
6
Table 29-15. FCNFG Field Descriptions (continued)
Section
MC9S12XE-Family Reference Manual Rev. 1.25
Table 29-16. FERCNFG Field Descriptions
29.3.2.6)
0
0
5
—
The FSFD bit allows the user to simulate a single bit fault during Flash array
EPVIOLIE
0
4
Description
Description
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2)
ERSVIE1
0
3
ERSVIE0
Section
Section
Section
0
2
29.3.2.8)
29.3.2.8)
29.3.2.8)
DFDIE
0
1
Section
SFDIE
29.3.2.7)
0
0
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