S912XET512J3VALR Freescale Semiconductor, S912XET512J3VALR Datasheet - Page 326

• Manufacturer Part Number: S912XET512J3VALR
• Description: 16-bit Microcontrollers - MCU 16 BIT,512K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S912XET512J3VALR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12XE
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-112
• Mounting Style: SMD/SMT

Chapter 8 S12X Debug (S12XDBGV3) Module
8.3.2.8.7
Read: Anytime. See
Write: If DBG not armed. See
8.3.2.8.8
Read: Anytime. See
Write: If DBG not armed. See
8.4
This section provides a complete functional description of the S12XDBG module. If the part is in secure
mode, the S12XDBG module can generate breakpoints but tracing is not possible.
326
Address: 0x002E
Address: 0x002F
Bits[15:8]
Bits[7:0]
Reset
Reset
Field
Field
7–0
7–0
W
W
R
R
Functional Description
Bit 15
Comparator Data High Mask Bits — The Comparator data high mask bits control whether the selected
comparator compares the data bus bits [15:8] to the corresponding comparator data compare bits. This register
is available only for comparators A and C.
0 Do not compare corresponding data bit
1 Compare corresponding data bit
Bit 7
Comparator Data Low Mask Bits — The Comparator data low mask bits control whether the selected
comparator compares the data bus bits [7:0] to the corresponding comparator data compare bits. This register
is available only for comparators A and C.
0 Do not compare corresponding data bit
1 Compare corresponding data bit
0
0
7
7
Debug Comparator Data High Mask Register (DBGXDHM)
Debug Comparator Data Low Mask Register (DBGXDLM)
Figure 8-20. Debug Comparator Data High Mask Register (DBGXDHM)
Figure 8-21. Debug Comparator Data Low Mask Register (DBGXDLM)
Table 8-29
Table 8-29
Bit 14
Bit 6
0
0
6
6
Table 8-29
Table 8-29
MC9S12XE-Family Reference Manual Rev. 1.25
for visible register encoding.
for visible register encoding.
Table 8-37. DBGXDHM Field Descriptions
Table 8-38. DBGXDLM Field Descriptions
Bit 13
Bit 5
0
0
5
5
for visible register encoding.
for visible register encoding.
Bit 12
Bit 4
0
0
4
4
Description
Description
Bit 11
Bit 3
0
0
3
3
Bit 10
Bit 2
0
0
2
2
Freescale Semiconductor
Bit 9
Bit 1
0
0
1
1
Bit 8
Bit 0
0
0
0
0