S912XET512J3VALR Freescale Semiconductor, S912XET512J3VALR Datasheet - Page 36

• Manufacturer Part Number: S912XET512J3VALR
• Description: 16-bit Microcontrollers - MCU 16 BIT,512K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S912XET512J3VALR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12XE
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-112
• Mounting Style: SMD/SMT

Chapter 1 Device Overview MC9S12XE-Family
Unimplemented RAM pages are mapped externally in expanded modes. Accessing unimplemented RAM
pages in single chip modes causes an illegal address reset if the MPU is not configured to flag an MPU
protection error in that range.
Accessing unimplemented FLASH pages in single chip modes causes an illegal address reset if the MPU
is not configured to flag an MPU protection error in that range.
The PARTID value should be referenced regarding the specific memory map for any given device. For
devices sharing the same part ID, the memory regions which are implemented on the larger device but not
supported on the smaller device are implemented but untested on that smaller device. These regions do not
appear as unimplemented in the memory map and do not result in an illegal address reset if erroneously
accessed.
From the above the following examples can be derived.
The 9S12XEP768 is currently only available as a 9S12XEP100 die, thus the unimplemented FLASH pages
are those of the 9S12XEP100 device map.
The 9S12XEQ384, 9S12XEG384, 9S12XES384 are currently only available as a 9S12XEQ512 die, thus
the unimplemented FLASH pages are those of the 9S12XEQ512 device map.
The 9S12XEG128 is currently only available as a 9S12XET256 die, thus the unimplemented FLASH
pages are those of the 9S12XET256 device map.
The range between 0x10_0000 and 0x13_FFFF is mapped to EEPROM resources. The actual EEPROM
and dataflash block sizes are listed in
which is neither used by EEPROM resources nor remapped to external resources via chip selects (see the
FTM/MMC descriptions for details). These ranges do not constitute unimplemented areas.
Accessing reserved registers within the 2K register space does not generate an illegal address reset.
The fixed 8K RAM default location in the global map is 0x0F_E000- 0x0F_FFFF. This is subject to
remapping when configuring the local address map for a larger RAM access range.
36
0xCC8x
0xCC9x
0xC48x
0xC08x
Part ID
Table 1-2. Unimplemented Range Mapping to Part ID
RAM_LOW
0x0F_C000
0x0F_0000
0x0F_0000
0x0F_8000
MC9S12XE-Family Reference Manual Rev. 1.25
Table
1-4. Within EEPROM resource range an address range exists
0x13_F000
0x13_F000
0x13_F000
0x13_F000
EE_LOW
B3, B2, B1S, B1N, B0
B3, B2, B1S, B1N, B0
B1S, B0(128K)
Flash Blocks
B1N, B1S, B0
Registers
2K
2K
2K
2K
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