MT29F128G08WAAC6 Micron, MT29F128G08WAAC6 Datasheet - Page 13

• Manufacturer Part Number: MT29F128G08WAAC6
• Description: NAND Flash Memory
• Manufacturer: Micron

Architecture
Figure 6:
Addressing
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16gb_nand_mlc_l52a__2.fm -Rev. D 5/08 EN
WE#
WP#
R/B#
I/Ox
CE#
ALE
RE#
CLE
NAND Flash Functional Block Diagram
control
Control
logic
These devices use NAND Flash electrical and command interfaces. Data, commands,
and addresses are multiplexed onto the same pins and received by I/O control circuits.
This provides a memory device with a low pin count. The commands received at the I/O
control circuits are latched by a command register and are transferred to control logic
circuits for generating internal signals to control device operations. The addresses are
latched by an address register and sent to a row decoder or a column decoder to select a
row address or a column address, respectively.
The data are transferred to or from the NAND Flash memory array, byte by byte (x8),
through a data register and a cache register. The cache register is closest to I/O control
circuits and acts as a data buffer for the I/O data, whereas the data register is closest to
the memory array and acts as a data buffer for the NAND Flash memory array operation.
The NAND Flash memory array is programmed and read in page-based operations and
is erased in block-based operations. During normal page operations, the data and cache
registers are tied together and act as a single register. During cache operations, the data
and cache registers operate independently to increase data throughput.
These devices also have a status register that reports the status of device operation.
NAND Flash devices do not contain dedicated address pins. Addresses are loaded using
a 5-cycle sequence as shown in Table 3 on page 15. See Figure 7 on page 14 for additional
memory mapping and addressing details.
I/O
Command register
Micron Confidential and Proprietary
Address register
Status register
13
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16, 32, 64, 128Gb NAND Flash Memory
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Column decode
Cache register
NAND Flash
Data register
(2 planes)
array
©2005 Micron Technology, Inc. All rights reserved.
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Architecture
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