MT29F128G08WAAC6 Micron, MT29F128G08WAAC6 Datasheet - Page 36

• Manufacturer Part Number: MT29F128G08WAAC6
• Description: NAND Flash Memory
• Manufacturer: Micron

PAGE READ CACHE MODE SEQUENTIAL 31h
PAGE READ CACHE MODE RANDOM 00h-31h
PAGE READ CACHE MODE LAST 3Fh
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16gb_nand_mlc_l52a__2.fm -Rev. D 5/08 EN
that the cache register is available and that the NAND Flash array is ready. At this point
data can be output from the cache register, beginning at column address 0, by toggling
RE#. The RANDOM DATA READ (05h-E0h) command can be used to change the column
address of the data being output by the device.
During device busy times,
READ STATUS (70h, 78h) and RESET (FFh). Until status register bit 5 = 1, the only valid
commands during PAGE READ CACHE MODE operations are READ STATUS (70h, 78h),
READ (00h), PAGE READ CACHE MODE (31h and 00h-31h), RANDOM DATA READ (05h-
E0h), and RESET (FFh).
The PAGE READ CACHE MODE SEQUENTIAL (31h) command reads the next sequential
page within a block into the data register while the previous page is output from the
cache register. To issue this command, write 31h to the command register.
After this command is issued, R/B# goes LOW (status register bits 6 and 5 = 00) for either
t
ister bits 6 and 5 = 10 to indicate that the cache register is available and that the specified
page is copying from the NAND Flash array to the data register. At this point data can be
output from the cache register by toggling RE# beginning at column address 0. The RAN-
DOM DATA READ (05h-E0h) command can be used to change the column address of the
data being output by the device.
Do not issue the 31h command after reading the last page of the block into the data reg-
ister. Instead, issue the 3Fh command. Crossing block boundaries with the PAGE READ
CACHE MODE SEQUENTIAL (31h) command is prohibited.
The PAGE READ CACHE MODE RANDOM (00h-31h) command reads the specified page
into the data register while the previous page is output from the cache register. To issue
this command, write 00h to the command register, then write 5 address cycles to the
address register. Conclude the sequence by writing 31h to the command register. The
column address in the address specified is ignored.
After this command is issued, R/B# goes LOW (status register bits 6 and 5 = 00) for either
t
ister bits 6 and 5 = 10 to indicate that the cache register is available and that the specified
page is copying from the NAND Flash array to the data register. At this point data can be
output from the cache register, beginning at column address 0, by toggling RE#. The
RANDOM DATA READ (05h-E0h) command can be used to change the column address
of the data being output by the device.
Do not issue the 00h-31h command to a different plane than the previously read page—
the plane-select bit must be set to the same value. If crossing plane boundaries is
required, complete the PAGE READ CACHE MODE operation using the 3Fh command,
then start a PAGE READ (00h-30h) operation to the new plane.
The PAGE READ CACHE MODE LAST (3Fh) command copies a page from the data regis-
ter to the cache register without beginning a new PAGE READ CACHE MODE operation.
To issue the PAGE READ CACHE MODE LAST command, write 3Fh to the command reg-
ister.
DCBSYR1 or
DCBSYR1 or
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Micron Confidential and Proprietary
DCBSYR2. After
DCBSYR2. After
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DCBSYR1 and
36
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DCBSYR1 or
DCBSYR1 or
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16, 32, 64, 128Gb NAND Flash Memory
Micron Technology, Inc., reserves the right to change products or specifications without notice.
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DCBSYR2, the only valid commands are
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DCBSYR2, R/B# goes HIGH and status reg-
DCBSYR2, R/B# goes HIGH and status reg-
Command Definitions
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