MT29F128G08WAAC6 Micron, MT29F128G08WAAC6 Datasheet - Page 18

• Manufacturer Part Number: MT29F128G08WAAC6
• Description: NAND Flash Memory
• Manufacturer: Micron

Address Input
Data Input
READ Operations
Ready/Busy#
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16gb_nand_mlc_l52a__2.fm -Rev. D 5/08 EN
Addresses are written to the address register on the rising edge of WE# when:
• CE# and CLE are LOW, and
• ALE is HIGH.
Addresses are input on I/O[7:0] only. Bits not part of the address space must be LOW.
The number of ADDRESS cycles required for each command varies. Refer to the com-
mand descriptions to determine addressing requirements. See Tables 6–7, starting on
page 22.
Data is written to the data register on the rising edge of WE# when:
• CE#, CLE, and ALE are LOW, and
• the device is not busy.
See Figure 72 on page 96 for additional data input details.
After a READ command is issued, data is transferred from the memory array to the data
register. R/B# goes LOW for
data is available in the data register, it is clocked out of the part by RE# going LOW. See
Figure 77 on page 99 for detailed timing information.
The READ STATUS (70h), or TWO-PLANE/MULTIPLE-DIE READ STATUS (78h) com-
mand or the R/B# signal can be used to determine when the device is ready.
If a controller is using a timing of 30ns or longer for
proper timing. If
(EDO) timing.
The R/B# output provides a hardware method of indicating the completion of PRO-
GRAM, ERASE, and READ operations. The signal requires a pull-up resistor for proper
operation. The signal is typically HIGH, and transitions to LOW after the appropriate
command is written to the device. The signal pin’s open-drain driver enables multiple
R/B# outputs to be OR-tied. The READ STATUS command can be used in place of R/B#.
Typically R/B# would be connected to an interrupt pin on the system controller (see
Figure 11 on page 19).
On the 32Gb devices, R/B# provides a status indication for the 16Gb section enabled by
CE#, and R/B2# does the same for the 16Gb section enabled by CE2#. R/B# and R/B2#
can be tied together, or they can be used separately to provide independent indications
for each 16Gb section.
On the 64Gb devices, R/B# provides a status indication for the 32Gb section enabled by
CE#, and R/B2# does the same for the 32Gb section enabled by CE2#. R/B# and R/B2#
can be tied together, or they can be used separately to provide independent indications
for each 32Gb section.
On the 128Gb device, R/B# provides a status indication for the 32Gb section enabled by
CE#, R/B2# provides a status indication for the 32Gb section enabled by CE2#, R/B3#
provides a status indication for the 32Gb section enabled by CE3#, and R/B4# provides a
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t
RC is less than 30ns, use Figure 74 on page 97 for extended data output
t
R and transitions HIGH after the transfer is complete. When
18
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16, 32, 64, 128Gb NAND Flash Memory
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RC, use Figure 73 on page 97 for
©2005 Micron Technology, Inc. All rights reserved.
Bus Operation
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