MT29F128G08WAAC6 Micron, MT29F128G08WAAC6 Datasheet - Page 41

• Manufacturer Part Number: MT29F128G08WAAC6
• Description: NAND Flash Memory
• Manufacturer: Micron

PROGRAM for INTERNAL DATA MOVE 85h-10h
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16gb_nand_mlc_l52a__2.fm -Rev. D 5/08 EN
After the READ for INTERNAL DATA MOVE (00h-35h) command has been issued and
R/B# goes HIGH, the PROGRAM for INTERNAL DATA MOVE (85h-10h) command can
be written to the command register. This command transfers the data from the cache
register to the data register and programming of the new destination page begins. The
sequence: 85h, destination address (5 cycles), then 10h, is written to the device. After 10h
is written, R/B# goes LOW while the control logic automatically programs the new page.
The READ STATUS command and bit 6 of the status register can be used instead of the
R/B# line to determine when the write is complete. Bit 0 of the status register indicates if
the operation was successful.
The RANDOM DATA INPUT (85h) command can be used during the PROGRAM for
INTERNAL DATA MOVE command sequence to modify a word or multiple words of the
original data. First, data is copied into the cache register using the 00h-35h command
sequence, then the RANDOM DATA INPUT (85h) command is written along with the
address of the data to be modified next. New data is input on the external data pins. This
copies the new data into the cache register.
When 10h is written to the command register, the original data plus the modified data is
transferred to the data register, and programming of the new page is started. The RAN-
DOM DATA INPUT command can be issued as many times as necessary before starting
the programming sequence with 10h (see Figures 24 and 25 on page 43).
Because INTERNAL DATA MOVE operations do not use external memory, ECC cannot
be used to check for errors before programming the data to a new page. This can lead to
a data error if the source page contains a bit error due to charge loss or charge gain. In
the case that multiple INTERNAL DATA MOVE operations are performed, these bit
errors may accumulate without correction. For this reason, it is highly recommended
that systems using INTERNAL DATA MOVE operations also use a robust ECC scheme
that exceeds the minimum required ECC.
If a RESET (FFh) command is issued during a PROGRAM for INTERNAL DATA MOVE
(85h-10h) operation while R/B# is LOW, the data in the shared-memory cells being pro-
grammed could become invalid. Interrupting a PROGRAM operation on one page could
corrupt the data in another page within the block being programmed.
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16, 32, 64, 128Gb NAND Flash Memory
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Command Definitions
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