MT29F128G08WAAC6 Micron, MT29F128G08WAAC6 Datasheet - Page 63

• Manufacturer Part Number: MT29F128G08WAAC6
• Description: NAND Flash Memory
• Manufacturer: Micron

TWO-PLANE PROGRAM for INTERNAL DATA MOVE 85h-11h-85h-10h
PDF: 09005aef8278ee3f / Source: 09005aef81f17540
16gb_nand_mlc_l52a__2.fm -Rev. D 5/08 EN
After a TWO-PLANE READ for INTERNAL DATA MOVE (00h-00h-35h) command is
issued, the data transferred from the source pages into the cache registers may be read
out by toggling RE#. Data is output sequentially from the column address originally
specified by the TWO-PLANE READ FOR INTERNAL DATA MOVE (00h-00h-35h) com-
mand, starting with plane 0.
A TWO-PLANE RANDOM DATA READ (06h-E0h) command can be used to select the
data transferred from the source pages of each plane. This command will change the
starting column address on only the plane being selected. The column address on the
plane moved from will remain unchanged from its previous location.
The memory device is now ready to accept the TWO-PLANE PROGRAM for INTERNAL
DATA MOVE (85h-11h-85h-10h) command.
Alternatively, two READ for INTERNAL DATA MOVE (00h-35h) commands may be
issued, each addressing different planes on the same die, prior to issuing the TWO-
PLANE PROGRAM for INTERNAL DATA MOVE (85h-11h-85h-10h) command.
After the TWO-PLANE READ for INTERNAL DATA MOVE (00h-00h-35h) command has
been issued and R/B# goes HIGH (or the status register bit 6 is “1”), the TWO-PLANE
PROGRAM for INTERNAL DATA MOVE (85h-11h-85h-10h) command is used. Pages
must be read from and programmed to the same plane.
First, write 85h to the command register, then write the first-plane destination address
(5 cycles), then write 11h to the command register. The 11h command is a “dummy”
command that informs the control logic that the first set of data for the first plane is
complete. No programming of the NAND Flash array occurs. R/B# goes LOW for
then returns HIGH. The READ STATUS (70h) command also indicates that the device is
ready when status register bit 6 is set to “1.”
The only valid commands during
(FFh).
After
plane destination address (5 cycles), and then write 10h to the command register. Data is
transferred from the cache registers to the data registers on the rising edge of WE#, and
programming begins on both planes.
R/B# goes LOW for the duration of array programming time,
ming and verification are complete, R/B# returns HIGH. The READ STATUS (70h) com-
mand also indicates that the device is ready when status register bit 6 is set to “1.” The
only valid commands during
RESET (FFh).
If the READ STATUS (70h) command indicates an error in the operation (status register
bit 0 is “1”), use the TWO-PLANE/MULTIPLE-DIE READ STATUS (78h) command
twice—once for each plane—to determine which plane operation failed.
If a RESET (FFh) command is issued during a TWO-PLANE PROGRAM for INTERNAL
DATA MOVE operation while R/B# is LOW, the data in the shared-memory cells being
programmed could become invalid. Interrupting a PROGRAM operation on one page
could corrupt the data in another page within the block being programmed.
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DBSY, write the 85h command to the command register. Then write the second-
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63
PROG are READ STATUS (70h and 78h) commands and
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DBSY are READ STATUS (70h and 78h) and RESET
16, 32, 64, 128Gb NAND Flash Memory
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Command Definitions
t
PROG. When program-
©2005 Micron Technology, Inc. All rights reserved.
t
DBSY,
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