MT29F128G08WAAC6 Micron, MT29F128G08WAAC6 Datasheet - Page 61

• Manufacturer Part Number: MT29F128G08WAAC6
• Description: NAND Flash Memory
• Manufacturer: Micron

PDF: 09005aef8278ee3f / Source: 09005aef81f17540
16gb_nand_mlc_l52a__2.fm -Rev. D 5/08 EN
To enter the TWO-PLANE PROGRAM PAGE CACHE MODE, write the 80h command to
the command register, write 5 ADDRESS cycles for the first plane, then write the data.
Serial data is loaded on consecutive WE# cycles, starting at the given address. Next, write
the 11h command. The 11h command is a “dummy” command that informs the control
logic that the first set of data for the first plane is complete. No programming of the
NAND Flash array occurs. R/B# goes LOW for
TUS command also indicates that the device is ready when status register bit 6 is set to
“1.”
The PROGRAM PAGE CACHE MODE command can cross block boundaries; it cannot
cross die boundaries.
The only valid commands during
(FFh).
After
for the second plane, then write the data. The CACHE WRITE (15h) command is written
after the second-plane data input is complete. Data is transferred from the cache regis-
ters to the data registers on the rising edge of WE#. R/B# goes LOW during this transfer
time. After the data has been copied into the data registers and R/B# returns HIGH,
memory array programming to both planes begins.
When R/B# returns HIGH, new data can be written to the cache registers by issuing
another TWO-PLANE PROGRAM PAGE CACHE MODE (80h-11h-80h-15h) sequence.
The time that R/B# stays LOW (
the previous operation. For the first cache operation,
for the data to be copied from the cache registers to the data registers. On the second
and subsequent TWO-PLANE PROGRAM PAGE CACHE MODE operations, transfer from
the cache registers to the data registers is delayed until the contents of the current data
registers have been programmed into the arrays.
If the R/B# pin is used to determine programming completion, the last operation of the
program sequence must use the TWO-PLANE PROGRAM PAGE (80h-11h-80h-10h)
command instead of the TWO-PLANE PROGRAM PAGE CACHE MODE (80h-11h-80h-
15h) command. If the TWO-PLANE PROGRAM PAGE CACHE MODE (80h-11h-80h-15h)
command is used for the last operation, then use READ STATUS (70h or 78h) to monitor
the operation's progress; status register bit 5 indicates when programming is complete.
To determine when the current TWO-PLANE PROGRAM PAGE CACHE MODE (80h-11h-
80h-10h) operation has completed, issue the READ STATUS (70h) command and check
status register bits 5 and 6. When the device is ready, use status register bit 0 to deter-
mine if the current operation passed and status register bit 1 to determine if the previous
operation passed. If either bit 0 = 1 or bit 1 = 1, indicating a failed operation, then use the
TWO-PLANE/MULTIPLE-DIE READ STATUS (78h) command twice—once for each
plane—to determine which current or previous plane operation failed. For more infor-
mation on status register bit definitions, see Table 11 on page 34.
During the serial data input for either plane, the RANDOM DATA INPUT (85h) com-
mand may be used any number of times to change the column address within that
plane.
If a RESET (FFh) command is issued during a TWO-PLANE PROGRAM PAGE CACHE
MODE operation while R/B# or bit 5 or bit 6 of the status register is LOW, the data in the
shared memory cells being programmed could become invalid. Interruption of a PRO-
GRAM operation on one page could corrupt the data in another page within the block
being programmed.
t
DBSY, write the 80h command to the command register, write 5 ADDRESS cycles
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61
t
CBSY) is determined by the actual programming time of
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t
DBSY are READ STATUS (70h and 78h) and RESET
16, 32, 64, 128Gb NAND Flash Memory
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t
DBSY, then returns HIGH. The READ STA-
t
CBSY duration is the time it takes
Command Definitions
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