MT29F128G08WAAC6 Micron, MT29F128G08WAAC6 Datasheet - Page 17

• Manufacturer Part Number: MT29F128G08WAAC6
• Description: NAND Flash Memory
• Manufacturer: Micron

Bus Operation
Control Signals
Commands
PDF: 09005aef8278ee3f / Source: 09005aef81f17540
16gb_nand_mlc_l52a__2.fm -Rev. D 5/08 EN
The bus on the MT29Fxxx devices is multiplexed. Data I/O, addresses, and commands
all share the same pins, I/O[7:0]. The 32Gb and 64Gb LGA packaged devices each have
two independent data I/O and command pads. These are I/O[7:0], CE#, WE#, RE#, CLE,
ALE, WP#, and I/O[7-2:0-2], CE2#, WE2#, RE2#, CLE2, ALE2, WP2#. This allows indepen-
dent data I/O, address, and command control for each half of a 32Gb or 64Gb device.
The 128Gb LGA packaged device has two independent data I/O and command pads.
These are I/O[7:0], CE#, CE3#, WE#, RE#, CLE, ALE, WP#, and I/O[7-2:0-2], CE2#, CE4#,
WE2#, RE2#, CLE2, ALE2, WP2#. This allows independent data I/O, address, and com-
mand control for each 32Gb portion of the 128Gb device.
The command sequence normally consists of a COMMAND LATCH cycle, ADDRESS
INPUT cycles, and one or more DATA cycles—either READ or WRITE.
CE#, WE#, RE#, CLE, ALE and WP# control Flash device READ and WRITE operations.
On the 32Gb devices, CE# and CE2# each control independent 16Gb arrays. On the 64Gb
devices, CE# and CE2# each control independent 32Gb arrays. On the 128Gb devices,
CE#, CE2#, CE3#, and CE4# each control independent 32Gb arrays. CE2#, CE#3, and
CE#4 function the same as CE# for their own arrays; all operations described for CE# also
apply to CE2#, CE3#, and CE4#.
CE# is used to enable the device. When CE# is LOW and the device is not in the busy
state, the Flash memory will accept command, address, and data information.
When the device is not performing an operation, the CE# pin is typically driven HIGH
and the device enters standby mode. The memory will enter standby if CE# goes HIGH
while data is being transferred and the device is not busy. This helps reduce power con-
sumption. See Figure 78 on page 100 and Figure 86 on page 106 for examples of CE#
“Don’t Care” operations.
The CE# “Don’t Care” operation enables the NAND Flash to reside on the same asyn-
chronous memory bus as other Flash or SRAM devices. Other devices on the memory
bus can then be accessed while the NAND Flash is busy with internal operations. This
capability is important for designs that require multiple NAND Flash devices on the
same bus.
A HIGH CLE signal indicates that a COMMAND cycle is taking place. A HIGH ALE signal
signifies that an ADDRESS INPUT cycle is occurring.
Commands are written to the command register on the rising edge of WE# when:
• CE# and ALE are LOW, and
• CLE is HIGH, and
• the device is not busy.
As exceptions, the device accepts the READ STATUS, TWO-PLANE/MULTIPLE-DIE
READ STATUS, and RESET commands when busy. Commands are transferred to the
command register on the rising edge of WE# (see Figure 70 on page 95). Commands are
input on I/O[7:0].
Micron Confidential and Proprietary
17
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16, 32, 64, 128Gb NAND Flash Memory
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
Bus Operation
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